Leandro Pereira edd18c8f5a arch: x86: Better document that CR0.WP will also be set when CR0.PG is ... Setting bit CR0.WP (bit 16) will inhibit supervisor threads from writing to RO pages. It's a necessary flag to be set, and the constant name CR0_PAGING_ENABLE didn't reflect the fact that the 16th bit was being set. Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>		2018-05-26 19:09:33 -04:00
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asm_inline.h	…
asm_inline_gcc.h	cleanup: rename fiber/task -> thread	2017-10-30 18:41:15 -04:00
cache_private.h	…
exception.h	x86: allow IDT vectors to be task gates	2017-07-25 11:32:36 -04:00
kernel_arch_data.h	arch: x86: Better document that CR0.WP will also be set when CR0.PG is	2018-05-26 19:09:33 -04:00
kernel_arch_func.h	arch: x86: Rename MSR-handling functions to conform to convention	2018-05-23 14:38:22 -04:00
kernel_arch_thread.h	debug: remove option GDB_INFO	2018-02-12 13:58:28 -08:00
kernel_event_logger_arch.h	…
mmustructs.h	x86: MMU: Memory domain implementation for x86	2017-11-07 12:22:43 -08:00
offsets_short_arch.h	…
swapstk.h	cleanup: rename fiber/task -> thread	2017-10-30 18:41:15 -04:00