Ulf Magnusson 3cb9018e23 arch: x86: Kconfig: Fix CACHE_LINE_SIZE default for CPU_ATOM ... With Zephyr's prefer-later-defaults behavior, the default value of CACHE_LINE_SIZE was always 0, because 'default 0' acts like 'default 0 if y'. Change the code to what was probably the intention (default to 0 unless CPU_ATOM). It looks like CACHE_LINE_SIZE is never used in the code when CACHE_LINE_SIZE_DETECT is on, so maybe things could be simplified further. Piggy-back some prompt style consistency cleanups. Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>		2018-07-12 23:08:43 -04:00
..
arc	arch: arc: add nsim support in soc	2018-07-10 19:05:13 -04:00
arm	arch: arm: mpu: fix _get_region_ap(.) function	2018-07-12 13:00:37 -05:00
common	gen_isr_tables: Delete the dead code accompanying .intList.num_isrs	2018-06-25 12:54:49 -07:00
nios2	cmake: LD: Specify the entry point in the linker scripts	2018-07-03 17:18:14 -04:00
posix	boards: native_posix: Add option to build with Address Sanitizer	2018-07-03 17:06:25 -04:00
riscv32	cmake: LD: Specify the entry point in the linker scripts	2018-07-03 17:18:14 -04:00
x86	arch: x86: Kconfig: Fix CACHE_LINE_SIZE default for CPU_ATOM	2018-07-12 23:08:43 -04:00
xtensa	cmake: LD: Specify the entry point in the linker scripts	2018-07-03 17:18:14 -04:00
CMakeLists.txt	arch: Cmake: Add __ZEPHYR_SUPERVISOR__ macro for arch files.	2018-05-15 17:48:18 +03:00
Kconfig	arch/Kconfig: Remove redundant 'default n' properties	2018-06-26 11:07:57 -05:00