OrgZephyr/zephyr
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zephyr/soc/riscv/riscv-privilege
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Carlo Caione 10061efdc4 riscv: Rework and cleanup Kconfig 
This patch is doing several things:

- Core ISA and extension Kconfig symbols have now a formalized name
  (CONFIG_RISCV_ISA_* and CONFIG_RISCV_ISA_EXT_*)

- a new Kconfig.isa file was introduced with the full set of extensions
  currently supported by the v2.2 spec

- a new Kconfig.core file was introduced to host all the RISCV cores
  (currently only E31)

- ISA and extensions settings are moved to SoC configuration files

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
 		2022-06-05 14:28:42 +02:00
..
andes_v5 riscv: Rework and cleanup Kconfig 2022-06-05 14:28:42 +02:00
common asm: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
gd32vf103 riscv: Rework and cleanup Kconfig 2022-06-05 14:28:42 +02:00
miv riscv: Rework and cleanup Kconfig 2022-06-05 14:28:42 +02:00
mpfs riscv: Rework and cleanup Kconfig 2022-06-05 14:28:42 +02:00
neorv32 riscv: Rework and cleanup Kconfig 2022-06-05 14:28:42 +02:00
sifive-freedom riscv: Rework and cleanup Kconfig 2022-06-05 14:28:42 +02:00
starfive_jh71xx riscv: Rework and cleanup Kconfig 2022-06-05 14:28:42 +02:00
telink_b91 riscv: Rework and cleanup Kconfig 2022-06-05 14:28:42 +02:00
virt riscv: Rework and cleanup Kconfig 2022-06-05 14:28:42 +02:00
CMakeLists.txt
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Kconfig soc: riscv: riscv-privilege: add support for mtvec vectored mode 2022-03-17 11:12:32 +01:00
Kconfig.defconfig
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Kconfig.soc
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