Dylan Hung 8b7ec919c8 soc: arm: aspeed: enable cache for AST10x0 series SOC ... Enable cache for AST10x0 series SOC in platform initialization. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>		2022-06-05 14:28:50 +02:00
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arm	soc: arm: aspeed: enable cache for AST10x0 series SOC	2022-06-05 14:28:50 +02:00
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