138 lines
3.8 KiB
ArmAsm
138 lines
3.8 KiB
ArmAsm
/*
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* Copyright (c) 2022 BayLibre, SAS
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/toolchain.h>
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#include <zephyr/linker/sections.h>
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#include <zephyr/kernel.h>
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#include <zephyr/sys/util.h>
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#include <offsets_short.h>
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#include <zephyr/arch/cpu.h>
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#include "asm_macros.inc"
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/* Convenience macros for loading/storing register states. */
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#define DO_CALLEE_SAVED(op, reg) \
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RV_E( op ra, _thread_offset_to_ra(reg) );\
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RV_E( op s0, _thread_offset_to_s0(reg) );\
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RV_E( op s1, _thread_offset_to_s1(reg) );\
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RV_I( op s2, _thread_offset_to_s2(reg) );\
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RV_I( op s3, _thread_offset_to_s3(reg) );\
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RV_I( op s4, _thread_offset_to_s4(reg) );\
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RV_I( op s5, _thread_offset_to_s5(reg) );\
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RV_I( op s6, _thread_offset_to_s6(reg) );\
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RV_I( op s7, _thread_offset_to_s7(reg) );\
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RV_I( op s8, _thread_offset_to_s8(reg) );\
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RV_I( op s9, _thread_offset_to_s9(reg) );\
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RV_I( op s10, _thread_offset_to_s10(reg) );\
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RV_I( op s11, _thread_offset_to_s11(reg) )
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#define DO_FP_CALLEE_SAVED(op, reg) \
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op fs0, _thread_offset_to_fs0(reg) ;\
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op fs1, _thread_offset_to_fs1(reg) ;\
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op fs2, _thread_offset_to_fs2(reg) ;\
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op fs3, _thread_offset_to_fs3(reg) ;\
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op fs4, _thread_offset_to_fs4(reg) ;\
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op fs5, _thread_offset_to_fs5(reg) ;\
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op fs6, _thread_offset_to_fs6(reg) ;\
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op fs7, _thread_offset_to_fs7(reg) ;\
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op fs8, _thread_offset_to_fs8(reg) ;\
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op fs9, _thread_offset_to_fs9(reg) ;\
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op fs10, _thread_offset_to_fs10(reg) ;\
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op fs11, _thread_offset_to_fs11(reg)
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GTEXT(z_riscv_switch)
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GTEXT(z_thread_mark_switched_in)
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GTEXT(z_riscv_configure_stack_guard)
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/* void z_riscv_switch(k_thread_t *switch_to, k_thread_t *switch_from) */
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SECTION_FUNC(TEXT, z_riscv_switch)
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/* Save the old thread's callee-saved registers */
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DO_CALLEE_SAVED(sr, a1)
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#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
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/* Assess whether floating-point registers need to be saved. */
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lb t0, _thread_offset_to_user_options(a1)
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andi t0, t0, K_FP_REGS
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beqz t0, skip_store_fp_callee_saved
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frcsr t0
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sw t0, _thread_offset_to_fcsr(a1)
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DO_FP_CALLEE_SAVED(fsr, a1)
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skip_store_fp_callee_saved:
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#endif /* CONFIG_FPU && CONFIG_FPU_SHARING */
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/* Save the old thread's stack pointer */
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sr sp, _thread_offset_to_sp(a1)
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/* Set thread->switch_handle = thread to mark completion */
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sr a1, ___thread_t_switch_handle_OFFSET(a1)
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/* Get the new thread's stack pointer */
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lr sp, _thread_offset_to_sp(a0)
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#if defined(CONFIG_THREAD_LOCAL_STORAGE)
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/* Get the new thread's tls pointer */
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lr tp, _thread_offset_to_tls(a0)
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#endif
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#if defined(CONFIG_PMP_STACK_GUARD)
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/*
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* Stack guard has priority over user space for PMP usage.
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* Preserve a0 across following call. s0 is not yet restored.
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*/
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mv s0, a0
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call z_riscv_pmp_stackguard_enable
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mv a0, s0
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#elif defined(CONFIG_USERSPACE)
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/*
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* When stackguard is not enabled, we need to configure the PMP only
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* at context switch time as the PMP is not in effect while inm-mode.
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* (it is done on every exception return otherwise).
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*/
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lb t0, _thread_offset_to_user_options(a0)
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andi t0, t0, K_USER
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beqz t0, not_user_task
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mv s0, a0
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call z_riscv_pmp_usermode_enable
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mv a0, s0
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not_user_task:
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#endif
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#if CONFIG_INSTRUMENT_THREAD_SWITCHING
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mv s0, a0
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call z_thread_mark_switched_in
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mv a0, s0
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#endif
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/* Restore the new thread's callee-saved registers */
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DO_CALLEE_SAVED(lr, a0)
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#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
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/* Determine if we need to restore floating-point registers. */
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lb t0, _thread_offset_to_user_options(a0)
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li t1, MSTATUS_FS_INIT
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andi t0, t0, K_FP_REGS
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beqz t0, no_fp
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/* Enable floating point access */
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csrs mstatus, t1
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/* Restore FP regs */
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lw t1, _thread_offset_to_fcsr(a0)
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fscsr t1
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DO_FP_CALLEE_SAVED(flr, a0)
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j 1f
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no_fp:
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/* Disable floating point access */
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csrc mstatus, t1
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1:
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#endif /* CONFIG_FPU && CONFIG_FPU_SHARING */
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/* Return to arch_switch() or _irq_wrapper() */
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ret
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