OrgZephyr/zephyr
OrgZephyr
/
zephyr
mirror of https://github.com/zephyrproject-rtos/zephyr.git
1
0
Fork 0
Code Issues Releases Wiki Activity
zephyr/arch/riscv
History
Carlo Caione 7a11d883cc riscv: Introduce RISCV_ALWAYS_SWITCH_THROUGH_ECALL 
Some early RISC-V SoCs have a problem when an `mret` instruction is used
outside a trap handler.

After the latest Zephyr RISC-V huge rework, the arch_switch code is
indeed calling `mret` when not in handler mode, breaking some early
RISC-V platforms.

Optionally restore the old behavior by adding a new
CONFIG_RISCV_ALWAYS_SWITCH_THROUGH_ECALL symbol.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
 		2022-07-04 18:18:10 +02:00
..
core riscv: Introduce RISCV_ALWAYS_SWITCH_THROUGH_ECALL 2022-07-04 18:18:10 +02:00
include riscv: Introduce RISCV_ALWAYS_SWITCH_THROUGH_ECALL 2022-07-04 18:18:10 +02:00
CMakeLists.txt
…
Kconfig riscv: Introduce RISCV_ALWAYS_SWITCH_THROUGH_ECALL 2022-07-04 18:18:10 +02:00
Kconfig.core riscv: Rework and cleanup Kconfig 2022-06-05 14:28:42 +02:00
Kconfig.isa riscv: Rework and cleanup Kconfig 2022-06-05 14:28:42 +02:00