25 lines
780 B
Plaintext
25 lines
780 B
Plaintext
# Copyright (c) 2018 Foundries.io Ltd
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# SPDX-License-Identifier: Apache-2.0
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config SOC_OPENISA_RV32M1_RISCV32
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bool "OpenISA RV32M1 RISC-V cores"
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select RISCV
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# The following select is due to limitations in the linker script.
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# (We can't make it a 'depends on' without causing a dependency loop).
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select XIP
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select HAS_RV32M1_LPUART
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select HAS_RV32M1_LPI2C
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select HAS_RV32M1_LPSPI
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select HAS_RV32M1_TPM
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select ATOMIC_OPERATIONS_C
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select VEGA_SDK_HAL
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select RISCV_SOC_INTERRUPT_INIT
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select CLOCK_CONTROL
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select HAS_RV32M1_FTFX
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select HAS_FLASH_LOAD_OFFSET
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select BUILD_OUTPUT_HEX
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help
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Enable support for OpenISA RV32M1 RISC-V processors. Choose
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this option to target the RI5CY or ZERO-RISCY core. This
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option should not be used to target either Arm core.
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