Ruibin Chang 97d2d7317c ITE soc/riscv/ite/it8xxx2/Kconfig: correct hw clock freq ... Correct SYS_CLOCK_HW_CYCLES_PER_SEC and SYS_CLOCK_TICKS_PER_SEC to match our real setting value for precise timing. Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>		2021-07-24 21:26:49 -04:00
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esp32c3	soc: riscv: esp32c3: use the new esp_rom prefix	2021-07-07 20:58:50 -04:00
litex-vexriscv	soc: riscv: litex-vexriscv: change CSR accessors	2020-10-02 11:36:16 +02:00
openisa_rv32m1	riscv: openisa_rv32m1: Fix booting of rv32m1_vega	2021-07-01 17:03:17 -05:00
riscv-ite	ITE soc/riscv/ite/it8xxx2/Kconfig: correct hw clock freq	2021-07-24 21:26:49 -04:00
riscv-privilege	soc: riscv: telink_b91: new Telink B91 (TLSR9) SoC system	2021-07-21 05:37:12 -04:00
CMakeLists.txt	…