zephyr/arch/riscv/core
Felipe Neves 7b09d031fa arch: riscv: added support for custom initialization of gp register
Plus added implementation for esp32c3 SoC.

Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-07-07 20:58:50 -04:00
..
offsets
pmp arch: riscv: Fix 10.4 violations 2021-04-10 09:59:37 -04:00
CMakeLists.txt
cpu_idle.c
fatal.c
irq_manage.c
irq_offload.c
isr.S
prep_c.c
reboot.c
reset.S
swap.S
thread.c arch: riscv: added support for custom initialization of gp register 2021-07-07 20:58:50 -04:00
tls.c
userspace.S