Dong Wang a6800cefb1 x86/cache: fix issues in arch dcache flush function ... Correct the wrong operand of clflush instruction. The old operand points to a location inside stack and doesn't work. The new one works well by taking linux kernel code as reference. End address instead of size should get round up Add Kconfig option to disable the usage of mfence intruction for SoC that has clfulsh but no mfence supported. Signed-off-by: Dong Wang <dong.d.wang@intel.com>		2021-07-23 16:22:07 -04:00
..
arc	ARC: save/restore accumulator registers on all ARCv2 HS CPUs by default	2021-07-06 15:17:26 -05:00
arm	cmake: Support coverage flags on all archs	2021-06-10 18:01:36 -04:00
arm64	arch: arm64: select SCHED_IPI_SUPPORTED for Armv8_R	2021-07-13 09:30:29 -04:00
common	cmake: Support coverage flags on all archs	2021-06-10 18:01:36 -04:00
nios2	arch: nios2: Fix 10.4 violations	2021-04-10 09:59:37 -04:00
posix	cmake: Support coverage flags on all archs	2021-06-10 18:01:36 -04:00
riscv	arch: riscv: added support for custom initialization of gp register	2021-07-07 20:58:50 -04:00
sparc	SPARC: Keep interrupts disabled during kernel init	2021-07-22 10:25:53 -04:00
x86	x86/cache: fix issues in arch dcache flush function	2021-07-23 16:22:07 -04:00
xtensa	xtensa: fix booting secondary cores on the dummy thread	2021-05-03 17:13:01 -04:00
CMakeLists.txt	…
Kconfig	arch/Kconfig: Remove stray tab from USERSPACE help	2021-07-15 22:58:28 +03:00