Manuel Arguelles b64d99091b arm: mpu: dsb after writing to SCTLR on MPU disable ... Execute data and instruction sync barriers after writing to SCTLR to disable the MPU, to ensure the registers are set before proceeding and that the new changes are seen by the instructions that follow. Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>		2022-07-26 11:09:42 +00:00
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aarch32	arm: mpu: dsb after writing to SCTLR on MPU disable	2022-07-26 11:09:42 +00:00
common	arch: migrate includes to <zephyr/...>	2022-05-06 19:57:22 +02:00
offsets	arch: cortex-m: Enable support for S2RAM	2022-07-11 15:26:26 +02:00