Manuel Arguelles b64d99091b arm: mpu: dsb after writing to SCTLR on MPU disable ... Execute data and instruction sync barriers after writing to SCTLR to disable the MPU, to ensure the registers are set before proceeding and that the new changes are seen by the instructions that follow. Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>		2022-07-26 11:09:42 +00:00
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arc	ARC: fix SMP race in ASM ARC interrupt handling code	2022-07-20 09:26:24 -05:00
arm	arm: mpu: dsb after writing to SCTLR on MPU disable	2022-07-26 11:09:42 +00:00
arm64	test,arch: fix few odd suffix include paths	2022-07-18 14:44:47 -04:00
common	gen_isr_tables.py: Move to scripts directory	2022-07-07 17:58:34 +00:00
mips	arch: mips: add mising braces to single line if statements	2022-07-06 11:00:45 -04:00
nios2	arch: comply to coding guidelines MISRA C:2012 Rule 14.4	2022-07-20 09:28:38 -05:00
posix	scripts: move user_wordsize.py to scripts/build/user_wordsize.py	2022-07-12 10:03:45 +02:00
riscv	riscv: Use IRQ vector table for vectored mode	2022-07-07 10:00:20 +02:00
sparc	asm: update files with <zephyr/...> include prefix	2022-05-09 12:45:29 -04:00
x86	arch: comply to coding guidelines MISRA C:2012 Rule 14.4	2022-07-20 09:28:38 -05:00
xtensa	intel_adsp: meteorlake: Initialize stack flush pointer SR	2022-07-25 16:00:22 -04:00
CMakeLists.txt	…
Kconfig	kconfig: guard MPU logging macros	2022-07-20 18:28:43 +02:00