64 lines
1.5 KiB
Plaintext
64 lines
1.5 KiB
Plaintext
# LPC LPC54XXX MCU line
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# Copyright (c) 2017, NXP
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# SPDX-License-Identifier: Apache-2.0
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choice
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prompt "LPC LPC54XXX MCU Selection"
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depends on SOC_SERIES_LPC54XXX
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config SOC_LPC54114_M4
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bool "SOC_LPC54114_M4"
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select CPU_CORTEX_M4
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_ARM_MPU
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select PLATFORM_SPECIFIC_INIT
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select CLOCK_CONTROL
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select HAS_MCUX_IAP_LEGACY
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config SOC_LPC54114_M0
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bool "SOC_LPC54114_M0"
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select CPU_CORTEX_M0PLUS
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select CPU_CORTEX_M_HAS_VTOR
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select CLOCK_CONTROL
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endchoice
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if SOC_SERIES_LPC54XXX
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config SOC_PART_NUMBER_LPC54114J256BD64
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bool
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config SOC_PART_NUMBER_LPC54XXX
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string
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default "LPC54114J256BD64" if SOC_PART_NUMBER_LPC54114J256BD64
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help
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This string holds the full part number of the SoC. It is a hidden
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option that you should not set directly. The part number selection
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choice defines the default value for this string.
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config SECOND_CORE_MCUX
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bool "Enable LPC54114 Cortex-M0 second core"
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depends on HAS_MCUX
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help
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Driver for second core startup
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config SECOND_IMAGE_MCUX
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depends on SECOND_CORE_MCUX
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string "Binary image of second core's code"
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help
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This points to the image file for the the binary code that will be
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used by the second core.
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config SECOND_CORE_BOOT_ADDRESS_MCUX
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depends on SECOND_CORE_MCUX
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hex "Address the second core will boot at"
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default 0x20010000
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help
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This is the address the second core will boot from. Additionally this
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address is where we will copy the SECOND_IMAGE to. We default this to
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the base of SRAM1.
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endif # SOC_SERIES_LPC54XXX
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