Piotr Mienkowski cdb6bfff1e soc: same70, samv71: free TRACESWO pin when unused ... Pin PB5 is part of ARM Cortex-M debug interface and by default configured to output TDO/TRACESWO signal. Disable TDO/TRACESWO function on PB5 pin when LOG_BACKEND_SWO is not enabled. This ultimately frees the pin to be used by standard SoC peripherals. Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>		2021-07-17 08:09:08 -04:00
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arm	soc: arm: mps2_an521: have separate configs for the 2 cores of AN521	2021-06-22 08:45:41 -04:00
atmel_sam	soc: same70, samv71: free TRACESWO pin when unused	2021-07-17 08:09:08 -04:00
atmel_sam0	Kconfig: `ROM_START_OFFSET` fix for samd5x	2021-05-27 15:57:05 -05:00
bcm_vk	…
common/cortex_m	soc: arm: nxp_imx: add rt117x support	2021-06-29 11:30:00 -04:00
cypress	soc: arm: cypress: psoc6: Enable Cortex-M4	2021-07-02 22:50:29 -04:00
infineon_xmc	…
microchip_mec	soc: Microchip: MEC172x initial submission	2021-07-01 13:34:06 -04:00
nordic_nrf	soc: nordic_nrf: Add HAS_HW_NRF_KMU config	2021-06-23 12:48:12 +02:00
nuvoton	…
nuvoton_npcx	soc: npcx: Improve npcx header Kconfig	2021-07-16 18:59:12 -04:00
nxp_imx	counter: Add counter support for rt600	2021-07-16 18:56:15 -04:00
nxp_kinetis	soc: arm: nxp: kinetis: ke1xf: add support for power management	2021-07-14 22:54:34 +03:00
nxp_lpc	boards: arm: Enable arduino serial port on lpcxpresso55s69	2021-06-12 08:55:31 -05:00
quicklogic_eos_s3	…
renesas_rcar	soc: renesas_rcar: gen3: enable L1 cache and branch prediction	2021-06-10 17:13:21 -04:00
silabs_exx32	soc: replace power/power.h with pm/pm.h	2021-05-05 18:35:49 -04:00
st_stm32	soc: arm: stm32l1: set voltage scaling to range1	2021-07-15 10:13:27 +03:00
ti_lm3s6965	…
ti_simplelink	soc: arm: cc32xx: Override Reboot implementation	2021-07-06 15:22:39 -05:00
xilinx_zynqmp	…
CMakeLists.txt	…
Kconfig	…