Piotr Mienkowski cdb6bfff1e soc: same70, samv71: free TRACESWO pin when unused ... Pin PB5 is part of ARM Cortex-M debug interface and by default configured to output TDO/TRACESWO signal. Disable TDO/TRACESWO function on PB5 pin when LOG_BACKEND_SWO is not enabled. This ultimately frees the pin to be used by standard SoC peripherals. Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>		2021-07-17 08:09:08 -04:00
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arc	arc: hsdk: add compiler options without check	2021-05-25 07:04:32 -05:00
arm	soc: same70, samv71: free TRACESWO pin when unused	2021-07-17 08:09:08 -04:00
arm64	soc: arm64: arm: fvp_base_r: define a strong pm_cpu_on() function	2021-07-13 09:30:29 -04:00
nios2	…
posix	posix: Add missing include	2021-04-27 13:17:36 -04:00
riscv	drivers: gpio: it8xxx2: add support for GPIO_VOLTAGE_ flags	2021-07-15 13:53:54 -05:00
sparc	…
x86	soc/x86: Clean up EHL kconfigs	2021-05-07 16:48:58 -04:00
xtensa	esp32: drivers: interrupt_controller: add interrupt allocation support	2021-07-16 07:19:28 -04:00
Kconfig	kconfig: soc and shield cleanup	2021-06-11 16:13:22 +02:00