202 lines
5.7 KiB
Plaintext
202 lines
5.7 KiB
Plaintext
# Nuvoton Cortex-M4 Embedded Controller
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# Copyright (c) 2020 Nuvoton Technology Corporation.
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# SPDX-License-Identifier: Apache-2.0
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config SOC_FAMILY_NPCX
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bool
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if SOC_FAMILY_NPCX
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config SOC_FAMILY
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string
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default "nuvoton_npcx"
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menuconfig NPCX_HEADER
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bool "Enable the output binary with NPCX binary header"
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help
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On NPCX series chip, the NPCX ROM code loads firmware image from flash
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to RAM by the firmware binary header setting. Enable this to invoke
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the 'ecst' which generates the NPCX firmware header.
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if NPCX_HEADER
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config NPCX_IMAGE_OUTPUT_BIN
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bool "Build npcx binary in BIN format"
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default y
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help
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Build a "raw" binary zephyr/zephyr.npcx.bin in the build directory.
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The name of this file can be customized with CONFIG_KERNEL_BIN_NAME.
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config NPCX_IMAGE_OUTPUT_HEX
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bool "Build npcx binary in HEX format"
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depends on NPCX_IMAGE_OUTPUT_BIN
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help
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Build an HEX binary zephyr/zephyr.npcx.hex in the build directory.
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This is generated from the npcx BIN image.
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The name of this file can be customized with CONFIG_KERNEL_BIN_NAME.
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config NPCX_HEADER_CHIP
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string
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default "npcx7m6" if SOC_NPCX7M6FB || SOC_NPCX7M6FC
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default "npcx7m7" if SOC_NPCX7M7FC
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default "npcx9m3" if SOC_NPCX9M3F
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default "npcx9m6" if SOC_NPCX9M6F
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choice NPCX_HEADER_SPI_MAX_CLOCK_CHOICE
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prompt "Clock rate to use for SPI flash"
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default NPCX_HEADER_SPI_MAX_CLOCK_20
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help
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This selects the max clock rate that will be used for loading firmware
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binary from flash to RAM.
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config NPCX_HEADER_SPI_MAX_CLOCK_20
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bool "SPI flash max clock rate of 20 MHz"
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config NPCX_HEADER_SPI_MAX_CLOCK_25
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bool "SPI flash max clock rate of 25 MHz"
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config NPCX_HEADER_SPI_MAX_CLOCK_33
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bool "SPI flash max clock rate of 33 MHz"
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depends on !SOC_SERIES_NPCX9
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config NPCX_HEADER_SPI_MAX_CLOCK_40
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bool "SPI flash max clock rate of 40 MHz"
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config NPCX_HEADER_SPI_MAX_CLOCK_50
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bool "SPI flash max clock rate of 50 MHz"
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endchoice
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config NPCX_HEADER_SPI_MAX_CLOCK
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int
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default 20 if NPCX_HEADER_SPI_MAX_CLOCK_20
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default 25 if NPCX_HEADER_SPI_MAX_CLOCK_25
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default 33 if NPCX_HEADER_SPI_MAX_CLOCK_33
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default 40 if NPCX_HEADER_SPI_MAX_CLOCK_40
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default 50 if NPCX_HEADER_SPI_MAX_CLOCK_50
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choice NPCX_HEADER_SPI_READ_MODE_CHOICE
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prompt "Reading mode used by the SPI flash"
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default NPCX_HEADER_SPI_READ_MODE_NORMAL
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help
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This sets the reading mode that can be used by the SPI flash.
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Reading modes supported are normal, fast, dual, and quad.
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config NPCX_HEADER_SPI_READ_MODE_NORMAL
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bool "SPI flash operates with normal reading mode"
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config NPCX_HEADER_SPI_READ_MODE_FAST
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bool "SPI flash operates with fast reading mode"
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config NPCX_HEADER_SPI_READ_MODE_DUAL
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bool "SPI flash operates with dual reading mode"
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config NPCX_HEADER_SPI_READ_MODE_QUAD
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bool "SPI flash operates with quad reading mode"
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endchoice
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config NPCX_HEADER_SPI_READ_MODE
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string
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default "normal" if NPCX_HEADER_SPI_READ_MODE_NORMAL
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default "fast" if NPCX_HEADER_SPI_READ_MODE_FAST
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default "dual" if NPCX_HEADER_SPI_READ_MODE_DUAL
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default "quad" if NPCX_HEADER_SPI_READ_MODE_QUAD
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choice NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_CHOICE
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prompt "Core clock to SPI flash clock ratio"
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default NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1
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help
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This sets the clock ratio (core clock / SPI clock)
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config NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1
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bool "NPCX SPI clock ratio 1"
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help
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The SPI flash clock has the same frequency as the core clock.
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config NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2
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bool "NPCX SPI clock ratio 2"
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help
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The core clock frequency is twice the flash clock frequency.
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endchoice
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config NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO
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int
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default 1 if NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1
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default 2 if NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2
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config NPCX_HEADER_ENABLE_HEADER_CRC
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bool "Enable header crc check"
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help
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When enabled, the header will be verified at boot using a crc
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checksum.
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config NPCX_HEADER_ENABLE_FIRMWARE_CRC
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bool "Enable firmware image crc check"
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help
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When enabled, the firmware image will be verified at boot using a
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crc checksum.
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choice NPCX_HEADER_FLASH_SIZE_CHOICE
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prompt "Flash size"
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default NPCX_HEADER_FLASH_SIZE_0P5M_1M if SOC_SERIES_NPCX7 || \
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SOC_SERIES_NPCX9
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default NPCX_HEADER_FLASH_SIZE_16M
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help
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This sets the SPI flash size.
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config NPCX_HEADER_FLASH_SIZE_0P5M_1M
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bool "SPI flash size 0.5M or 1M Bytes"
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help
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The SPI flash size is 0.5M or 1M Bytes.
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config NPCX_HEADER_FLASH_SIZE_2M
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bool "SPI flash size 2M Bytes"
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help
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The SPI flash size is 2M Bytes.
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config NPCX_HEADER_FLASH_SIZE_4M
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bool "SPI flash size 4M Bytes"
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help
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The SPI flash size is 4M Bytes.
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config NPCX_HEADER_FLASH_SIZE_8M
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bool "SPI flash size 8M Bytes"
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help
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The SPI flash size is 8M Bytes.
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config NPCX_HEADER_FLASH_SIZE_16M
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bool "SPI flash size 16M Bytes"
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help
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The SPI flash size is 16M Bytes.
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endchoice
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config NPCX_HEADER_FLASH_SIZE
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int
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default 1 if NPCX_HEADER_FLASH_SIZE_0P5M_1M
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default 2 if NPCX_HEADER_FLASH_SIZE_2M
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default 4 if NPCX_HEADER_FLASH_SIZE_4M
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default 8 if NPCX_HEADER_FLASH_SIZE_8M
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default 16 if NPCX_HEADER_FLASH_SIZE_16M
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endif # NPCX_HEADER
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# Select SoC Part No. and configuration options
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source "soc/arm/nuvoton_npcx/*/Kconfig.soc"
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config SOC_POWER_MANAGEMENT
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bool "System Power Management in NPCX family"
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depends on SOC_FAMILY_NPCX
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help
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This option enables the board to implement SoC-specific power
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management policies whenever the kernel becomes idle. The power
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management subsystem will restore to the active state until an
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wake-up event is received no matter the system timer is expired or
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the other signals occurred such as GPIO, host access, and so on.
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config SOC_POWER_MANAGEMENT_TRACE
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bool "Trace System Power Management in NPCX family"
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depends on SOC_POWER_MANAGEMENT
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help
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Internal config to enable runtime power management traces.
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endif # SOC_FAMILY_NPCX
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