41 lines
1.1 KiB
C
41 lines
1.1 KiB
C
/*
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* Copyright (c) 2019 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __MEC_SOC_H
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#define __MEC_SOC_H
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#ifndef _ASMLANGUAGE
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/*
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* MEC172x includes the ARM single precision FPU and the ARM MPU with
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* eight regions. Zephyr has an in-tree CMSIS header located in the arch
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* include hierarchy that includes the correct ARM CMSIS core_xxx header
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* from hal_cmsis based on the k-config CPU selection.
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* The Zephyr in-tree header does not provide all the symbols ARM CMSIS
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* requires. Zephyr does not define CMSIS FPU present and defaults CMSIS
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* MPU present to 0. We define these two symbols here based on our k-config
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* selections. NOTE: Zephyr in-tree CMSIS defines the Cortex-M4 hardware
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* revision to 0. At this time ARM CMSIS does not appear to use the hardware
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* revision in any macros.
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*/
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#define __FPU_PRESENT CONFIG_CPU_HAS_FPU
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#define __MPU_PRESENT CONFIG_CPU_HAS_ARM_MPU
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#include "reg/mec172x_regs.h"
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#include <sys/util.h>
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#include "../common/soc_gpio.h"
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#include "../common/soc_pins.h"
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#include "../common/soc_espi_channels.h"
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#include "../common/soc_espi_saf.h"
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uint32_t soc_get_core_clock(void);
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#endif
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#endif
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