a10ce7561f
Zephyr kernel masks interrupts before calling the SoC PM sleep entry point. On the Cortex-Mx family this prevents wake from peripheral interrupts. The SoC PM layer requires interrupts to wake the SoC and must prevent the CPU from vectoring to an interrup until PM exit. The SoC does this by setting ARM NVIC PRIMASK to 1 and BASEPRI to 0. On return to the kernel SoC sets PRIMASK to 0 allowing ISR's to fire. In addition the MEC HW only clears its peripheral sleep enables if the CPU vectors to an ISR. On wake we clear the MEC PCR sleep control register which clears all the peripheral sleep enables so peripherals will be active before exiting the SoC PM layer. Signed-off-by: Scott Worley <scott.worley@microchip.com> |
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| .. | ||
| CMakeLists.txt | ||
| Kconfig.defconfig.mec1501hsz | ||
| Kconfig.defconfig.series | ||
| Kconfig.series | ||
| Kconfig.soc | ||
| device_power.c | ||
| device_power.h | ||
| linker.ld | ||
| power.c | ||
| soc.c | ||
| soc.h | ||
| timing.c | ||