408 lines
14 KiB
C
408 lines
14 KiB
C
/*
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* Copyright (c) 2020 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file Header containing definitions for MCHP eSPI SAF
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*/
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#ifndef _SOC_ESPI_SAF_H_
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#define _SOC_ESPI_SAF_H_
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#include <stdint.h>
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#include <sys/util.h>
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#include <soc.h>
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#define MCHP_SAF_MAX_FLASH_DEVICES 2U
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/*
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* SAF hardware state machine timings
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* poll timeout is in 32KHz clock periods
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* poll interval is in AHB clock(48MHz) units.
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* suspend resume interval is in 32KHz clock periods.
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* consecutive read timeout is in AHB clock periods.
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* suspend check delay is in AHB clock(48MHz) periods.
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*/
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#define MCHP_SAF_FLASH_POLL_TIMEOUT 0x28000U
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#define MCHP_SAF_FLASH_POLL_INTERVAL 0U
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#define MCHP_SAF_FLASH_SUS_RSM_INTERVAL 8U
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#define MCHP_SAF_FLASH_CONSEC_READ_TIMEOUT 2U
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#define MCHP_SAF_FLASH_SUS_CHK_DELAY 0U
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/* Default SAF Map of eSPI TAG numbers to master numbers */
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#define MCHP_SAF_TAG_MAP0_DFLT 0x23221100
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#define MCHP_SAF_TAG_MAP1_DFLT 0x77677767
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#define MCHP_SAF_TAG_MAP2_DFLT 0x00000005
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/*
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* Default QMSPI clock divider and chip select timing.
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* QMSPI master clock is 48MHz AHB clock.
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*/
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#define MCHP_SAF_QMSPI_CLK_DIV 2U
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#define MCHP_SAF_QMSPI_CS_TIMING 0x03000101U
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/* SAF QMSPI programming */
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#define MCHP_SAF_QMSPI_NUM_FLASH_DESCR 6U
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#define MCHP_SAF_QMSPI_CS0_START_DESCR 0U
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#define MCHP_SAF_QMSPI_CS1_START_DESCR \
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(MCHP_SAF_QMSPI_CS0_START_DESCR + MCHP_SAF_QMSPI_NUM_FLASH_DESCR)
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/* SAF engine requires start indices of descriptor chains */
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#define MCHP_SAF_CM_EXIT_START_DESCR 12U
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#define MCHP_SAF_CM_EXIT_LAST_DESCR 13U
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#define MCHP_SAF_POLL_STS_START_DESCR 14U
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#define MCHP_SAF_POLL_STS_END_DESCR 15U
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#define MCHP_SAF_NUM_GENERIC_DESCR 4U
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/* QMSPI descriptors 12-15 for all SPI flash devices */
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/* #define SAF_QMSPI_DESCR12 0x0002D40E */
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/*
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* QMSPI descriptors 12-13 are exit continuous mode
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*/
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#define MCHP_SAF_EXIT_CM_DESCR12 \
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(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_ONES | \
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MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
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MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \
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MCHP_QMSPI_C_XFR_UNITS_1 | \
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MCHP_QMSPI_C_NEXT_DESCR(13) | \
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MCHP_QMSPI_C_XFR_NUNITS(1))
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#define MCHP_SAF_EXIT_CM_DESCR13 \
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(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \
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MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_EN | \
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MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_CLOSE | \
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MCHP_QMSPI_C_XFR_UNITS_1 | \
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MCHP_QMSPI_C_NEXT_DESCR(0) | \
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MCHP_QMSPI_C_XFR_NUNITS(9) | \
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MCHP_QMSPI_C_DESCR_LAST)
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/*
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* QMSPI descriptors 14-15 are poll 16-bit flash status
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* Transmit one byte opcode at 1X (no DMA).
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* Receive two bytes at 1X (no DMA).
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*/
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#define MCHP_SAF_POLL_DESCR14 \
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(MCHP_QMSPI_C_IFM_1X | MCHP_QMSPI_C_TX_DATA | \
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MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
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MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \
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MCHP_QMSPI_C_XFR_UNITS_1 | \
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MCHP_QMSPI_C_NEXT_DESCR(15) | \
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MCHP_QMSPI_C_XFR_NUNITS(1))
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#define MCHP_SAF_POLL_DESCR15 \
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(MCHP_QMSPI_C_IFM_1X | MCHP_QMSPI_C_TX_DIS | \
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MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_EN | \
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MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_CLOSE | \
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MCHP_QMSPI_C_XFR_UNITS_1 | \
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MCHP_QMSPI_C_NEXT_DESCR(0) | \
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MCHP_QMSPI_C_XFR_NUNITS(2) | \
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MCHP_QMSPI_C_DESCR_LAST)
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/* SAF Pre-fetch optimization mode */
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#define MCHP_SAF_PREFETCH_MODE MCHP_SAF_FL_CFG_MISC_PFOE_DFLT
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#define MCHP_SAF_CFG_MISC_PREFETCH_EXPEDITED 0x03U
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/*
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* SAF Opcode 32-bit register value.
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* Each byte contain a SPI flash 8-bit opcode.
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* NOTE1: opcode value of 0 = flash does not support this operation
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* NOTE2:
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* SAF Opcode A
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* op0 = SPI flash write-enable opcode
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* op1 = SPI flash program/erase suspend opcode
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* op2 = SPI flash program/erase resume opcode
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* op3 = SPI flash read STATUS1 opcode
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* SAF Opcode B
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* op0 = SPI flash erase 4KB sector opcode
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* op1 = SPI flash erase 32KB sector opcode
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* op2 = SPI flash erase 64KB sector opcode
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* op3 = SPI flash page program opcode
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* SAF Opcode C
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* op0 = SPI flash read 1-4-4 continuous mode opcode
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* op1 = SPI flash op0 mode byte value for non-continuous mode
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* op2 = SPI flash op0 mode byte value for continuous mode
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* op3 = SPI flash read STATUS2 opcode
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*/
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#define MCHP_SAF_OPCODE_REG_VAL(op0, op1, op2, op3) \
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(((uint32_t)(op0)&0xffU) | (((uint32_t)(op1)&0xffU) << 8) | \
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(((uint32_t)(op2)&0xffU) << 16) | (((uint32_t)(op3)&0xffU) << 24))
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/*
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* SAF Flash Config CS0/CS1 QMSPI descriptor indices register value
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* e = First QMSPI descriptor index for enter continuous mode chain
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* r = First QMSPI descriptor index for continuous mode read chain
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* s = Index of QMSPI descriptor in continuous mode read chain that
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* contains the data length field.
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*/
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#define MCHP_SAF_CS_CFG_DESCR_IDX_REG_VAL(e, r, s) (((uint32_t)(e)&0xfU) | \
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(((uint32_t)(r)&0xfU) << 8) | (((uint32_t)(s)&0xfU) << 12))
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/* W25Q128 SPI flash device connected size in bytes */
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#define MCHP_W25Q128_SIZE (16U * 1024U * 1024U)
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/*
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* Six QMSPI descriptors describe SPI flash opcode protocols.
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* Example: W25Q128
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*/
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/* Continuous mode read: transmit-quad 24-bit address and mode byte */
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#define MCHP_W25Q128_CM_RD_D0 \
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(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DATA | \
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MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
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MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \
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MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(4))
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/* Continuous mode read: transmit-quad 4 dummy clocks with I/O tri-stated */
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#define MCHP_W25Q128_CM_RD_D1 \
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(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \
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MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
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MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \
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MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(2))
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/* Continuous mode read: read N bytes */
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#define MCHP_W25Q128_CM_RD_D2 \
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(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \
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MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_EN | \
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MCHP_QMSPI_C_RX_DMA_4B | MCHP_QMSPI_C_CLOSE | \
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MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(0) | \
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MCHP_QMSPI_C_DESCR_LAST)
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/* Enter Continuous mode: transmit-single CM quad read opcode */
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#define MCHP_W25Q128_ENTER_CM_D0 \
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(MCHP_QMSPI_C_IFM_1X | MCHP_QMSPI_C_TX_DATA | \
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MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
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MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \
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MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(1))
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/* Enter Continuous mode: transmit-quad 24-bit address and mode byte */
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#define MCHP_W25Q128_ENTER_CM_D1 \
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(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DATA | \
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MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
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MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \
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MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(4))
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/* Enter Continuous mode: read-quad 3 bytes */
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#define MCHP_W25Q128_ENTER_CM_D2 \
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(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \
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MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
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MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_CLOSE | \
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MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(3) | \
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MCHP_QMSPI_C_DESCR_LAST)
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#define MCHP_W25Q128_OPA MCHP_SAF_OPCODE_REG_VAL(0x06U, 0x75U, 0x7aU, 0x05U)
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#define MCHP_W25Q128_OPB MCHP_SAF_OPCODE_REG_VAL(0x20U, 0x52U, 0xd8U, 0x02U)
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#define MCHP_W25Q128_OPC MCHP_SAF_OPCODE_REG_VAL(0xebU, 0xffU, 0xa5U, 0x35U)
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/* W25Q128 STATUS2 bit[7] == 0 part is NOT in suspend state */
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#define MCHP_W25Q128_POLL2_MASK 0xff7fU
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/*
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* SAF Flash Continuous Mode Prefix register value
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* b[7:0] = continuous mode prefix opcode
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* b[15:8] = continuous mode prefix opcode data
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* Some SPI flash devices require a prefix command before
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* they will enter continuous mode.
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* A zero value means the SPI flash does not require a prefix
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* command.
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*/
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#define MCHP_W25Q128_CONT_MODE_PREFIX_VAL 0U
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#define MCHP_W25Q128_FLAGS 0U
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/* W25Q256 SPI flash device connected size in bytes */
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#define MCHP_W25Q256_SIZE (32U * 1024U * 1024U)
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/*
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* Six QMSPI descriptors describe SPI flash opcode protocols.
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* W25Q256 device.
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*/
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/* Continuous Mode Read: Transmit-quad opcode plus 32-bit address */
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#define MCHP_W25Q256_CM_RD_D0 \
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(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DATA | \
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MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
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MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \
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MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(5))
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#define MCHP_W25Q256_CM_RD_D1 \
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(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \
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MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
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MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \
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MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(2))
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#define MCHP_W25Q256_CM_RD_D2 \
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(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \
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MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_EN | \
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MCHP_QMSPI_C_RX_DMA_4B | MCHP_QMSPI_C_CLOSE | \
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MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(0) | \
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MCHP_QMSPI_C_DESCR_LAST)
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/* Enter Continuous mode: transmit-single CM quad read opcode */
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#define MCHP_W25Q256_ENTER_CM_D0 \
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(MCHP_QMSPI_C_IFM_1X | MCHP_QMSPI_C_TX_DATA | \
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MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
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MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \
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MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(1))
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/* Enter Continuous mode: transmit-quad 32-bit address and mode byte */
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#define MCHP_W25Q256_ENTER_CM_D1 \
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(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DATA | \
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MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
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MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \
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MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(5))
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/* Enter Continuous mode: read-quad 3 bytes */
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#define MCHP_W25Q256_ENTER_CM_D2 \
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(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \
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MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
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MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_CLOSE | \
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MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(3) | \
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MCHP_QMSPI_C_DESCR_LAST)
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#define MCHP_W25Q256_OPA SAF_OPCODE_REG_VAL(0x06U, 0x75U, 0x7aU, 0x05U)
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#define MCHP_W25Q256_OPB SAF_OPCODE_REG_VAL(0x20U, 0x52U, 0xd8U, 0x02U)
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#define MCHP_W25Q256_OPC SAF_OPCODE_REG_VAL(0xebU, 0xffU, 0xa5U, 0x35U)
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#define MCHP_W25Q256_POLL2_MASK 0xff7fU
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#define MCHP_W25Q256_CONT_MODE_PREFIX_VAL 0U
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#define MCHP_W25Q256_FLAGS 0U
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/* SAF Flash Config CS0 QMSPI descriptor indices */
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#define MCHP_CS0_CFG_DESCR_IDX_REG_VAL \
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MCHP_SAF_CS_CFG_DESCR_IDX_REG_VAL(3U, 0U, 2U)
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/* SAF Flash Config CS1 QMSPI descriptor indices */
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#define MCHP_CS1_CFG_DESCR_IDX_REG_VAL \
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MCHP_SAF_CS_CFG_DESCR_IDX_REG_VAL(9U, 6U, 8U)
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#define MCHP_SAF_HW_CFG_FLAG_FREQ 0x01U
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#define MCHP_SAF_HW_CFG_FLAG_CSTM 0x02U
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#define MCHP_SAF_HW_CFG_FLAG_CPHA 0x04U
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/* enable SAF prefetch */
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#define MCHP_SAF_HW_CFG_FLAG_PFEN 0x10U
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/* Use expedited prefetch instead of default */
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#define MCHP_SAF_HW_CFG_FLAG_PFEXP 0x20U
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/*
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* Override the default tag map value when this bit is set
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* in a tag_map[].
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*/
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#define MCHP_SAF_HW_CFG_TAGMAP_USE BIT(31)
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struct espi_saf_hw_cfg {
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uint32_t qmspi_freq_hz;
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uint32_t qmspi_cs_timing;
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uint8_t qmspi_cpha;
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uint8_t flags;
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uint32_t generic_descr[MCHP_SAF_NUM_GENERIC_DESCR];
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uint32_t tag_map[MCHP_ESPI_SAF_TAGMAP_MAX];
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};
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/*
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* SAF local flash configuration.
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* SPI flash device size in bytes
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* SPI opcodes for SAF Opcode A register
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* SPI opcodes for SAF Opcode B register
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* SPI opcodes for SAF Opcode C register
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* QMSPI descriptors describing SPI opcode transmit and
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* data read.
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* SAF controller Poll2 Mast value specific for this flash device
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* SAF continuous mode prefix register value for those flashes requireing
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* a prefix byte transmitted before the enter continuous mode command.
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* Start QMSPI descriptor numbers.
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* miscellaneous flags.
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*/
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/* Flags */
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#define MCHP_FLASH_FLAG_ADDR32 BIT(0)
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struct espi_saf_flash_cfg {
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uint32_t flashsz;
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uint32_t opa;
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uint32_t opb;
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uint32_t opc;
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uint16_t poll2_mask;
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uint16_t cont_prefix;
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uint16_t cs_cfg_descr_ids;
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uint16_t flags;
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uint32_t descr[MCHP_SAF_QMSPI_NUM_FLASH_DESCR];
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};
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/*
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* 17 flash protection regions
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* Each region is described by:
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* SPI start address. 20-bits = bits[31:12] of SPI address
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* SPI limit address. 20-bits = bits[31:12] of last SPI address
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* 8-bit bit map of eSPI master write-erase permission
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* 8-bit bit map of eSPI maste read permission
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* eSPI master numbers 0 - 7 correspond to bits 0 - 7.
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*
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* Protection region lock:
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* One 32-bit register with bits[16:0] -> protection regions 16:0
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*
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* eSPI Host maps threads by a tag number to master numbers.
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* Thread numbers are 4-bit
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* Master numbers are 3-bit
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* Master number Thread numbers Description
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* 0 0h, 1h Host PCH HW init
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* 1 2h, 3h Host CPU access(HW/BIOS/SMM/SW)
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* 2 4h, 5h Host PCH ME
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* 3 6h Host PCH LAN
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* 4 N/A Not defined/used
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* 5 N/A EC Firmware portal access
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* 6 9h, Dh Host PCH IE
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* 7 N/A Not defined/used
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*
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* NOTE: eSPI SAF specification allows master 0 (Host PCH HW) full
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* access to all protection regions.
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*
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* SAF TAG Map registers 0 - 2 map eSPI TAG values 0h - Fh to
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* the three bit master number. Each 32-bit register contains 3-bit
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* fields aligned on nibble boundaries holding the master number
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* associated with the eSPI tag (thread) number.
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* A master value of 7h in a field indicates a non-existent map entry.
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*
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* bit map of registers to program
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* b[2:0] = TAG Map[2:0]
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* b[20:4] = ProtectionRegions[16:0]
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* bit map of PR's to lock
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* b[20:4] = ProtectionRegions[16:0]
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*
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*/
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#define MCHP_SAF_PR_FLAG_ENABLE 0x01U
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#define MCHP_SAF_PR_FLAG_LOCK 0x02U
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#define MCHP_SAF_MSTR_HOST_PCH 0U
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#define MCHP_SAF_MSTR_HOST_CPU 1U
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#define MCHP_SAF_MSTR_HOST_PCH_ME 2U
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#define MCHP_SAF_MSTR_HOST_PCH_LAN 3U
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#define MCHP_SAF_MSTR_RSVD4 4U
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#define MCHP_SAF_MSTR_EC 5U
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#define MCHP_SAF_MSTR_HOST_PCH_IE 6U
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struct espi_saf_pr {
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uint32_t start;
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uint32_t size;
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uint8_t master_bm_we;
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uint8_t master_bm_rd;
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uint8_t pr_num;
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uint8_t flags; /* bit[0]==1 is lock the region */
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};
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struct espi_saf_protection {
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size_t nregions;
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const struct espi_saf_pr *pregions;
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};
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#endif /* _SOC_ESPI_SAF_H_ */
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