65 lines
1.8 KiB
C
65 lines
1.8 KiB
C
/*
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* Copyright (c) 2019 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_INTEL_ADSP_COMMON_SOC_H_
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#define ZEPHYR_SOC_INTEL_ADSP_COMMON_SOC_H_
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#include <string.h>
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#include <errno.h>
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#include <zephyr/linker/sections.h>
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#include <adsp_interrupt.h>
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/* DSP Wall Clock Timers (0 and 1) */
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#define DSP_WCT_IRQ(x) \
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SOC_AGGREGATE_IRQ((22 + x), CAVS_L2_AGG_INT_LEVEL2)
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#define DSP_WCT_CS_TA(x) BIT(x)
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#define DSP_WCT_CS_TT(x) BIT(4 + x)
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extern void z_soc_mp_asm_entry(void);
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extern void soc_mp_startup(uint32_t cpu);
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extern void soc_start_core(int cpu_num);
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extern bool soc_cpus_active[CONFIG_MP_MAX_NUM_CPUS];
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/* Legacy cache APIs still used in a few places */
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#define z_soc_cached_ptr(p) arch_xtensa_cached_ptr(p)
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#define z_soc_uncached_ptr(p) arch_xtensa_uncached_ptr(p)
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/**
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* @brief Halts and offlines a running CPU
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*
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* Enables power gating on the specified CPU, which cannot be the
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* current CPU or CPU 0. The CPU must be idle; no application threads
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* may be runnable on it when this function is called (or at least the
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* CPU must be guaranteed to reach idle in finite time without
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* deadlock). Actual CPU shutdown can only happen in the context of
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* the idle thread, and synchronization is an application
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* responsibility. This function will hang if the other CPU fails to
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* reach idle.
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*
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* @note On older cAVS hardware, core power is controlled by the host.
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* This function must still be called for OS bookkeeping, but it is
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* insufficient without application coordination (and careful
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* synchronization!) with the host x86 environment.
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*
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* @param id CPU to halt, not current cpu or cpu 0
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* @return 0 on success, -EINVAL on error
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*/
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int soc_adsp_halt_cpu(int id);
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static ALWAYS_INLINE void z_idelay(int n)
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{
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while (n--) {
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__asm__ volatile("nop");
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}
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}
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#endif /* ZEPHYR_SOC_INTEL_ADSP_COMMON_SOC_H_ */
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