zephyr/soc/xtensa/intel_adsp/common/include
Tomasz Lissowski 61cb7d4358 adsp: hda: accept 16 byte alignment for HDA buffer size
HDA DMA driver uses an excessive value of 128 bytes as required alignment
for DMA buffer size. This may result in the correct buffer size (e.g.
32-byte aligned, which is DT-compliant) being silently truncated before
writing it into DGBS register. This patch changes the requirement to the
value implied by DGBS register format (effectively reduces to 16 bytes).

Signed-off-by: Tomasz Lissowski <tomasz.lissowski@intel.com>
2024-01-03 18:59:55 +00:00
..
_soc_inthandlers.h
adsp-vectors.h
adsp_clk.h adsp: clk: ace: select ipll if wovrco is unavailable 2023-09-18 10:35:23 +01:00
adsp_debug_window.h
cavs-idc.h
cavstool.h
cpu_init.h intel_adsp: Initialize threadptr register 2023-05-25 18:23:39 -04:00
debug_helpers.h
intel_adsp_hda.h adsp: hda: accept 16 byte alignment for HDA buffer size 2024-01-03 18:59:55 +00:00
intel_adsp_ipc.h intel_adsp: Do not include device_runtime header 2023-10-27 10:51:14 +02:00
intel_adsp_ipc_devtree.h
manifest.h
mem_window.h intel_adsp: mem_window: reinitialize after idle exit 2023-06-22 06:14:57 -04:00
soc.h intel_adsp: remove deprecated cache macros 2023-06-23 11:14:08 -04:00
soc_util.h