29 lines
865 B
Plaintext
29 lines
865 B
Plaintext
# Copyright (c) 2018 Foundries.io Ltd
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# SPDX-License-Identifier: Apache-2.0
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# The OpenISA RV32M1 SoC directory in riscv supports the RISC-V
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# cores on OpenISA RV32M1 SoCs.
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#
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# The Zephyr "soc" abstraction isn't a great fit here. These SoCs (in
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# the strict physical sense of "systems on chip") also contain Arm
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# cores, so this type of "soc" doesn't really belong to a single "arch".
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#
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# However, due to constraints imposed by Zephyr's file hierarchy
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# conventions, those "other" cores would need to be supported under a
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# different soc subdirectory, e.g. soc/arm instead of soc/riscv.
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if SOC_OPENISA_RV32M1_RISCV32
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choice
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prompt "OpenISA RV32M1 RISC-V Core Selection"
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config SOC_OPENISA_RV32M1_RI5CY
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bool "OpenISA RV32M1 RI5CY core"
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config SOC_OPENISA_RV32M1_ZERO_RISCY
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bool "OpenISA RV32M1 ZERO-RISCY core"
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endchoice
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endif # SOC_OPENISA_RV32M1_RISCV32
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