# Copyright (c) 2018 Foundries.io Ltd
# SPDX-License-Identifier: Apache-2.0

# The OpenISA RV32M1 SoC directory in riscv supports the RISC-V
# cores on OpenISA RV32M1 SoCs.
#
# The Zephyr "soc" abstraction isn't a great fit here. These SoCs (in
# the strict physical sense of "systems on chip") also contain Arm
# cores, so this type of "soc" doesn't really belong to a single "arch".
#
# However, due to constraints imposed by Zephyr's file hierarchy
# conventions, those "other" cores would need to be supported under a
# different soc subdirectory, e.g. soc/arm instead of soc/riscv.

if SOC_OPENISA_RV32M1_RISCV32

choice
	prompt "OpenISA RV32M1 RISC-V Core Selection"

config SOC_OPENISA_RV32M1_RI5CY
	bool "OpenISA RV32M1 RI5CY core"

config SOC_OPENISA_RV32M1_ZERO_RISCY
	bool "OpenISA RV32M1 ZERO-RISCY core"

endchoice

endif  # SOC_OPENISA_RV32M1_RISCV32