71 lines
1.4 KiB
C
71 lines
1.4 KiB
C
/*
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* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc/rtc_cntl_reg.h>
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#include <soc/timer_group_reg.h>
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#include <soc/gpio_reg.h>
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#include <soc/syscon_reg.h>
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#include <soc/system_reg.h>
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#include <soc/cache_memory.h>
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#include "hal/soc_ll.h"
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#include <riscv/interrupt.h>
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#include <soc/interrupt_reg.h>
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#include <soc/periph_defs.h>
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#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
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#include <zephyr/kernel_structs.h>
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#include <string.h>
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#include <zephyr/toolchain/gcc.h>
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#include <soc.h>
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#include <zephyr/arch/riscv/arch.h>
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#define ESP32C3_INTSTATUS_SLOT1_THRESHOLD 32
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void arch_irq_enable(unsigned int irq)
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{
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esp_intr_enable(irq);
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}
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void arch_irq_disable(unsigned int irq)
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{
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esp_intr_disable(irq);
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}
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int arch_irq_is_enabled(unsigned int irq)
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{
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bool res = false;
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uint32_t key = irq_lock();
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if (irq < 32) {
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res = esp_intr_get_enabled_intmask(0) & BIT(irq);
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} else {
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res = esp_intr_get_enabled_intmask(1) & BIT(irq - 32);
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}
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irq_unlock(key);
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return res;
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}
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uint32_t soc_intr_get_next_source(void)
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{
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uint32_t status;
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uint32_t source;
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status = REG_READ(INTERRUPT_CORE0_INTR_STATUS_0_REG) &
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esp_intr_get_enabled_intmask(0);
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if (status) {
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source = __builtin_ffs(status) - 1;
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} else {
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status = REG_READ(INTERRUPT_CORE0_INTR_STATUS_1_REG) &
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esp_intr_get_enabled_intmask(1);
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source = (__builtin_ffs(status) - 1 + ESP32C3_INTSTATUS_SLOT1_THRESHOLD);
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}
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return source;
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}
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