1af8f2700b
Add support for configuring FlexSPI1 clock speed to RT5xx soc initialization, so that memory present on FlexSPI1 can be accessed. Note that FlexSPI1 is referred to as FlexSPI2 in the dts files for this SOC. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com> |
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| arc | ||
| arm | ||
| arm64 | ||
| mips | ||
| nios2 | ||
| posix | ||
| riscv | ||
| sparc | ||
| x86 | ||
| xtensa | ||
| Kconfig | ||