Build kconfig with -DKBUILD_NO_NLS by default and disable compiler
warning on Mac OS when building the host tools.
Change-Id: I76a2b5ab6b6b1c0bbe2dc2b31e3bd651fd05948e
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Updated board to arduino_101 and updated nanokernel_objects.c
NANO_CPU_INT_REGISTER macro args.
Change-Id: I5281a84138ef031ae82cdd80ab617f94b3f712af
Signed-off-by: Javier B Perez Hernandez <javier.b.perez.hernandez@linux.intel.com>
If the remote handler tries to send a message back with wait enabled
it can lead to a deadlock.
Change-Id: Ife6eae29c10e8937abd1b6511ee605f7786c6a7a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The while loop on the status bit was unnecessary as we will get
a separate invocation of the ISR for every message. We also ensure
that the global status register bits for the channel being serviced
are cleared before exiting. Fixes an issue where some messages
would be dropped or repeated.
Some runtime checks that shouldn't happen in practice have been moved
to assertions.
Change-Id: Iedd28ae15522c7b9f59ef34fa9fa8b4e24e6be14
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
It's unclear why the carriage returns were moved to the begnning and
not the end.
Change-Id: Ic6bda55c7537538c47477e6c44f5e4c1534573d4
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This implements the newly introduced APIs to manipulate line controls
for UART.
This also implements the driver command API as setting baud rate
may require setting the DLF.
Change-Id: I80634aa3fbd4a3223c46edb61417123e36f439dd
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds 2 new APIs to the serial/uart drivers:
() One is to control the serial line, such as RTS and CTS.
() Another one is to allow driver to expose hardware specific functions
to apps. This is needed as some hardware may have extra registers to
set for baud rate.
To keep the code size small, these features are disabled by default.
Change-Id: I15c000ce68a0a490dcfd3493b2fe9bc51fa974fa
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This moves the baud rate and options fields out of the UART driver
config struct and into the driver data struct. This will allow
changing baud rate and options at runtime in the future.
Change-Id: I62ddea2f95e634f2d60eeb9537f960799fc9301f
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The UART on Quark SE and D2000 supports fractional clock divider.
It is used to limit frequency error for supported baud rates.
Change-Id: I1f39a95db09f4a5a4116edc700a10e4b9ecfa2bd
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
When the SDK is updated usually it comes with new versions of the
compiler causing issues with the toolchain not finding libraries.
This will get the version from the compiler and sets the path
accordingly.
Change-Id: I854c57bb082ae8136eebdd0ae7a8c151c1d699c8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Avoid issues with variables having leading/trailing spaces.
Change-Id: I9e51197c1428a9eb701a73ee55f3a726486660d3
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Avoid issues with variables having quotes and leading/trailing spaces.
Additionally, set KERN_TYPE to micro.
Change-Id: Id3f5aeca6844292bbb537f443bd36f191432fe58
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
First look for a custom linker file defined by a config variable, if
not defined, look in the board directory. Finally look in the SoC
directory.
This adds flexibility and enhances modularity allowing a board to define
the linker the script instead of the SoC specific one.
Change-Id: Id44aa7d0e93d97234163ec858e2cfefe09768a08
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The semantics of this value is that it allows for the use of IRQ lines
0 through CONFIG_NUM_IRQS - 1.
Change-Id: I0287da931b06253065f4fba076e9a949dcb3cf53
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Too many entries were being created in this table. It needs to
create indexes starting from 16 to CONFIG_NUM_IRQS - 1, since IRQS 0-15
are reserved for CPU exceptions and are not handled through this
mechanism.
generic_arc was still using the old C-based table which is
incompatible with the static IRQ implementation. An attempt was made
to move the SW IRQ table to arch/arc/core, but linker issues were
encountered and this will be done in another patch.
With CONFIG_NUM_IRQS set to 68 on Quark SE, inspection of binary
with objdump -x reveals that we are generating table entries:
00000000 g O .isr_irq16 00000000 _sw_isr_table
00000000 w O .gnu.linkonce.isr_irq16 00000000 _isr_irq16
00000000 w O .gnu.linkonce.isr_irq17 00000000 _isr_irq17
00000000 w O .gnu.linkonce.isr_irq18 00000000 _isr_irq18
...
00000000 w O .gnu.linkonce.isr_irq67 00000000 _isr_irq67
Which is exactly what we need.
Change-Id: I8ca1682128ae67e2a24642791b7ce31ebca759bf
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Fixes the routine names referenced in the INT_LATENCY_BENCHMARK
kconfig option description.
Change-Id: I74c67a8f54cfc3b0ce75fc390d7ab6bd39561d6f
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
The routines _int_latency_start() and _int_latency_stop() have been
replaced by macros that evaluate to nothing when the kernel config
option INT_LATENCY_BENCHMARK is not enabled thereby giving a performance
boost to the x86 versions of irq_lock() and and irq_unlock().
Change-Id: Iabfa7bf001f5b8396e7bcf5eebd6b1aa342bac46
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Fixes a build warning caused by using the incorrect printf
identifier for a parameter of type size_t.
Change-Id: I03ecc245de366e7de07eb2b49a03f69af087090c
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
The ARC is an architecture that supports tickless idle in
nanokernel-only systems, and it thus must signal this to the build
system.
Change-Id: I96b0a4e8f78b2ea67d2f1b3384e94a32d8eb80e8
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
An architecture that supports tickless idle in the nanokernel can allow
selecting TICKLESS_IDLE by forcing NANOKERNEL_TICKLESS_IDLE_SUPPORTED to
be enabled.
Change-Id: I4e45b619c599913d40b7bc19902094fb361b1e3b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Re-applying this patch, which was lost when moving to kbuild:
commit 64c0f13f9380 ("kconfig: remove useless tickless idle dependency")
Author: Benjamin Walsh <benjamin.walsh@windriver.com>
Date: Mon May 11 15:13:46 2015 -0400
kconfig: remove useless tickless idle dependency
TICKLESS_IDLE_THRESH depends on TICKLESS_IDLE, which depends on
ADVANCED_POWER_MANAGEMENT, which itself already depends on
MICROKERNEL. There is thus no point in having TICKLESS_IDLE_THRESH
depend on MICROKERNEL.
Change-Id: I95edcc7b927dd122b80f376c96233decdcc9afab
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Change-Id: Id2ee328458c5a1be944e90c34bbc2158464be325
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Modified interrupt handling and idle code to enter and exit tickless
idle mode.
Change-Id: I3461ab6dba30003a4317027fc50a3ba07e830015
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
The architectures need to add support for it in their nano_cpu_idle()
and nano_cpu_atomic_idle() implementations, as well as in their
interrupt entry and exit code.
Change-Id: I44a241c56e624dc8e32e08db29a84489314cd7a4
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
CONFIG_NUM_IRQS expresses the total number of available interrupt
lines in the system, and is used to generate a vector table.
On ARC, the vector table is assembled from two parts, _VectorTable
for the first 16 entries (reserved for CPU exceptions), and
_IrqVectorTable for the remainder. The code that creates _IrqVectorTable
was not taking this into consideration and was 16 entries too big.
Change-Id: I676c8534274de8782178f3773bc53a817b89481f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
On ARC the IRQ and exception vectors are just one big array of
function pointers placed at the very beginning of the binary in ROM.
Vectors 0-15 are for CPU exceptions, 16-255 for interrupts.
In Zephyr these have been logically split into an execption table
followed immediately by the IRQ table, specified in the ARC linker.cmd.
However, the exception vector table defined in Zephyr had only 14
entries so the IRQ table was misaligned by 8 bytes. This went undetected
for some time as in the default configuration every entry in the IRQ
table pointed to the common demux function _isr_enter().
This patch correctly ensures that the IRQ table begins at address
0x40000040 instead of 0x40000038 like it had been.
Change-Id: I3b548df0dcabeb9d986ecd6a41e593bd02e3bd73
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Causes problems for large values of CONFIG_NUM_IRQS.
Some inconsistencies have been noted in how CONFIG_NUM_IRQS is
used on these platforms, with bugs filed. This patch preserves
existing behavior and has been shown to generate the same number
of table entries for both arches using objdump.
Change-Id: I1d3ac5466978acb56e88a6dc3cbe7cc09431e94d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The production version is slightly different than the internal
development board, so the pin mux description has been updated.
Change-Id: I0235ed9eb480a1fd713843dd1b3b5c7856e7132b
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Let the SoC decide the number of the IRQs. Fixes a bug where
Quark SE gets the default instead of the declared value in the SoC
Kconfig.
Change-Id: I978c923fbe2a0737ace27ec951bc3a46e8976584
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
_IrqVectorTable was renamed to _irq_vector_table
Change-Id: I1488bebc7d8174c08f3ce2dc8bcace6ef567aad6
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
We moved away from quark_d2000_ref_board and use crb for this board.
Change-Id: Ida1fb1675134c4eff7ecd9bf2e1cd1338df7635c
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Update the crosstool-ng .config files to build the most recent
gcc compiler (5.2.0) and update the configuration of the xtools
variant to use this compiler.
Change-Id: I8c895943a9db8637abf294da36df35040ae7527f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The option is used in the code but was never declared.
Change-Id: I17552c225936652e9208f53a884311eb81cb79a6
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Shorten the name and remove the vendor prefix. No need to add
vendor to board names.
Change-Id: I68d441121c4034276706da63d7e5420ddf317149
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Rename class in pci_dev_info struct to allow to use C++ compilers.
Updated drivers to use new struct.
Change-Id: I17b94cb7bc094bccd615c8389a28589bfa90cab8
Signed-off-by: Javier B Perez Hernandez <javier.b.perez.hernandez@linux.intel.com>
Even though the OS is 32-bit, 64-bit BARs can still be mapped into
32-bit address space.
64-bit BARs occupy two entries instead of one, so the offset of a BAR
isn't necessarily its index multiplied by 4. To cope with that, hold an
extra offset field in the lookup structure.
Only 3 bits are required for index as well as the offset since the there
are up to 6 BARs.
Change-Id: I0d4955a3aca70b7fc81a1df06ab5f9f45793c70f
Signed-off-by: Ido Yariv <idox.yariv@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Ido Yariv <ido@wizery.com>
Anas Nashif