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zephyr/soc/riscv/riscv-privilege/sifive-freedom/Kconfig.defconfig.series

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license: cleanup: add SPDX Apache-2.0 license identifier Update the files which contain no license information with the 'Apache-2.0' SPDX license identifier. Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of Zephyr, which is Apache version 2. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-04-06 21:08:09 +08:00
# SPDX-License-Identifier: Apache-2.0
riscv: freedom: rename RISCV32 to RISCV This code is common to 32- and 64-bit builds. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2019-07-19 11:05:53 +08:00
if SOC_SERIES_RISCV_SIFIVE_FREEDOM
riscv32: added support for the SiFive Freedom E310 SOC The SiFive Freedom E310 SOC follows the riscv privilege architecture specification and hence is declared within the riscv privilege SOC family. It also provides support for a riscv Platform Level Interrupt Controller (PLIC) Change-Id: I19ff0997eacc248f48444fc96566a105c6c02663 Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-03-15 05:15:59 +08:00
config SOC_SERIES
riscv: Rename the FE310 SoC to Sifive Freedom FE310 is the name of one SoC out of a range of products in the SiFive Freedom line. The FE310 SoC port in Zephyr is compatible with all of these products, so rename the SoC to SiFive Freedom Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2018-08-16 06:41:21 +08:00
default "sifive-freedom"
riscv32: added support for the SiFive Freedom E310 SOC The SiFive Freedom E310 SOC follows the riscv privilege architecture specification and hence is declared within the riscv privilege SOC family. It also provides support for a riscv Platform Level Interrupt Controller (PLIC) Change-Id: I19ff0997eacc248f48444fc96566a105c6c02663 Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-03-15 05:15:59 +08:00
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 32768
config RISCV_SOC_INTERRUPT_INIT
default y
config RISCV_HAS_CPU_IDLE
default y
config RISCV_HAS_PLIC
default y
interrupt: Convert RISC-V plic to use multi-level irq support Utilize the multi-level irq infrastructure and replace custom handling for PLIC on riscv-privilege SoCs. The old code offset IRQs in drivers and various places with RISCV_MAX_GENERIC_IRQ. Instead utilize Zephyr's encoded IRQ and replace offsets in drivers with the IRQ define from DTS. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-09 12:01:37 +08:00
config 2ND_LVL_ISR_TBL_OFFSET
default 12
config 2ND_LVL_INTR_00_OFFSET
default 11
config MAX_IRQ_PER_AGGREGATOR
default 52
riscv32: added support for the SiFive Freedom E310 SOC The SiFive Freedom E310 SOC follows the riscv privilege architecture specification and hence is declared within the riscv privilege SOC family. It also provides support for a riscv Platform Level Interrupt Controller (PLIC) Change-Id: I19ff0997eacc248f48444fc96566a105c6c02663 Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-03-15 05:15:59 +08:00
config NUM_IRQS
default 64
riscv: freedom: rename RISCV32 to RISCV This code is common to 32- and 64-bit builds. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2019-07-19 11:05:53 +08:00
endif # SOC_SERIES_RISCV_SIFIVE_FREEDOM