zephyr/soc/riscv
Adam Jeliński 86ca5ff562 m2gl025_miv: Adjust frequencies and performance
The default frequency for this board in Renode is 66 MHz. This needs to
be even with `SYS_CLOCK_HW_CYCLES_PER_SEC` to avoid such problems as in
the #31726 issue.

Unfortunately, the difference in these values was helpful for some tests
that are failing with 66 MHz set in both places. It created artificial
boost in certain circumstances.

The frequencies in the default Renode platform description (`.repl`)
file for MI-V were overridden with 4 MHz value that seems to be better
tolerated based on testing. The `SYS_CLOCK_HW_CYCLES_PER_SEC` was
adjusted as well.

To solve the rest of the issues, `cpu PerformanceInMips` was set to 4.
It seems tests are completed faster with such a value.

This commit fixes #31726.

Signed-off-by: Adam Jeliński <ajelinski@antmicro.com>
2021-02-09 19:41:27 -05:00
..
litex-vexriscv soc: riscv: litex-vexriscv: change CSR accessors 2020-10-02 11:36:16 +02:00
openisa_rv32m1 riscv: add support for thread local storage 2020-10-24 10:52:00 -07:00
riscv-ite drivers/i2c: add i2c driver on it8xxx2 platform 2021-01-15 11:22:57 -05:00
riscv-privilege m2gl025_miv: Adjust frequencies and performance 2021-02-09 19:41:27 -05:00
CMakeLists.txt