zephyr/arch/riscv32/soc/riscv-privilege/fe310/Kconfig.defconfig.series

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if SOC_SERIES_RISCV32_FE310
config SOC_SERIES
string
default "fe310"
config SYS_CLOCK_HW_CYCLES_PER_SEC
int
default 32768
config RISCV_SOC_INTERRUPT_INIT
bool
default y
config RISCV_HAS_CPU_IDLE
bool
default y
config RISCV_HAS_PLIC
bool
default y
config NUM_IRQS
int
default 64
config XIP
bool
default y
config RISCV_ROM_BASE_ADDR
hex
default 0x20400000
config RISCV_ROM_SIZE
hex
default 0xC00000
config RISCV_RAM_BASE_ADDR
hex
default 0x80000000
config RISCV_RAM_SIZE
hex
default 0x4000
endif # SOC_SERIES_RISCV32_FE310