2017-04-28 02:25:20 +08:00
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#include <arm/armv7-m.dtsi>
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/ {
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cpus {
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2017-07-16 02:57:32 +08:00
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#address-cells = <1>;
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#size-cells = <0>;
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2017-04-28 02:25:20 +08:00
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cpu@0 {
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2017-07-16 02:57:32 +08:00
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device_type = "cpu";
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2017-04-28 02:25:20 +08:00
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compatible = "arm,cortex-m3";
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2017-07-16 02:57:32 +08:00
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reg = <0>;
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2017-04-28 02:25:20 +08:00
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};
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};
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2017-07-21 20:43:01 +08:00
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sram0: memory@20000000 {
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2017-07-21 23:57:58 +08:00
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device_type = "memory";
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2017-07-20 20:59:29 +08:00
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compatible = "mmio-sram";
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2017-04-28 02:25:20 +08:00
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reg = <0x20000000 (64*1024)>;
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};
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2017-07-21 20:43:01 +08:00
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flash0: flash@0 {
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2018-09-21 07:39:55 +08:00
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compatible = "soc-nv-flash";
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2017-04-28 02:25:20 +08:00
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reg = <0x00000000 (256*1024)>;
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};
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soc {
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2018-11-09 19:53:08 +08:00
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uart0: uart@4000c000 {
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2017-04-29 00:34:06 +08:00
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compatible = "ti,stellaris-uart";
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2018-11-09 19:53:08 +08:00
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reg = <0x4000c000 0x4c>;
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2017-04-29 00:34:06 +08:00
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interrupts = <5 3>;
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status = "disabled";
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2017-05-17 10:10:47 +08:00
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label = "UART_0";
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2017-04-29 00:34:06 +08:00
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};
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2018-11-09 19:53:08 +08:00
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uart1: uart@4000d000 {
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2017-04-29 00:34:06 +08:00
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compatible = "ti,stellaris-uart";
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2018-11-09 19:53:08 +08:00
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reg = <0x4000d000 0x4c>;
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2017-04-29 00:34:06 +08:00
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interrupts = <6 3>;
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status = "disabled";
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2017-05-17 10:10:47 +08:00
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label = "UART_1";
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2017-04-29 00:34:06 +08:00
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};
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2018-11-09 19:53:08 +08:00
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uart2: uart@4000e000 {
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2017-04-29 00:34:06 +08:00
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compatible = "ti,stellaris-uart";
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2018-11-09 19:53:08 +08:00
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reg = <0x4000e000 0x4c>;
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2017-04-29 00:34:06 +08:00
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interrupts = <33 3>;
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status = "disabled";
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2017-05-17 10:10:47 +08:00
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label = "UART_2";
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2017-04-29 00:34:06 +08:00
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};
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2017-04-28 02:25:20 +08:00
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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