OrgZephyr/zephyr
OrgZephyr
/
zephyr
mirror of https://github.com/zephyrproject-rtos/zephyr.git
1
0
Fork 0
Code Issues Releases Wiki Activity
zephyr/soc/x86/apollo_lake/dts_fixup.h

41 lines
1.9 KiB
C
Raw Normal View History

arch/x86/soc: add SoC configuration for Apollo Lake This adds the SoC configuration for Apollo Lake. This is based on the Atom configuration. Origin: Original Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-07-17 09:37:14 +08:00
/*
gpio: intel_apl: rework driver for pin_mask callback To avoid confusion, callbacks using ordinal pin numbers is going to be reverted. So the driver has to be re-worked to expose multiple devices so each device has 32 pins. Also fixes #12765 Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-01-30 11:34:41 +08:00
* Copyright (c) 2018-2019 Intel Corporation Inc.
arch/x86/soc: add SoC configuration for Apollo Lake This adds the SoC configuration for Apollo Lake. This is based on the Atom configuration. Origin: Original Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-07-17 09:37:14 +08:00
*
* SPDX-License-Identifier: Apache-2.0
*/
/* SoC level DTS fixup file */
drivers/gpio/gpio_intel_apl: remove dependency on shared interrupts The GPIO driver for the Intel Apollo Lake has so many pins it has to export ten devices to shoehorn its one device into the GPIO API. The current implementation uses the shared IRQ driver because these pseudodevices all share one IRQ. However, since the GPIO driver is aware of all the possible interrupt sources, it's smaller and faster (and not even messy) to handle it internally, so this patch eliminates the dependency on the shared IRQ driver. Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-04-22 11:59:40 +08:00
#define DT_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
#define DT_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS
#define DT_RAM_SIZE CONFIG_SRAM_SIZE
#define DT_ROM_SIZE CONFIG_FLASH_SIZE
#define DT_IOAPIC_BASE_ADDRESS DT_INTEL_IOAPIC_FEC00000_BASE_ADDRESS
#define DT_APL_GPIO_BASE_ADDRESS_N DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_0
#define DT_APL_GPIO_BASE_ADDRESS_NW DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_1
#define DT_APL_GPIO_BASE_ADDRESS_W DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_2
#define DT_APL_GPIO_BASE_ADDRESS_SW DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_3
#define DT_APL_GPIO_IRQ DT_INTEL_APL_GPIO_D0C50000_IRQ_0
#define DT_APL_GPIO_IRQ_PRIORITY DT_INTEL_APL_GPIO_D0C50000_IRQ_0_PRIORITY
#define DT_APL_GPIO_IRQ_SENSE DT_INTEL_APL_GPIO_D0C50000_IRQ_0_SENSE
#define DT_APL_GPIO_MEM_SIZE_N DT_INTEL_APL_GPIO_D0C50000_SIZE_0
#define DT_APL_GPIO_MEM_SIZE_NW DT_INTEL_APL_GPIO_D0C50000_SIZE_1
#define DT_APL_GPIO_MEM_SIZE_W DT_INTEL_APL_GPIO_D0C50000_SIZE_2
#define DT_APL_GPIO_MEM_SIZE_SW DT_INTEL_APL_GPIO_D0C50000_SIZE_3
#define DT_APL_GPIO_LABEL_N_0 DT_INTEL_APL_GPIO_D0C50000_LABEL "_N_0"
#define DT_APL_GPIO_LABEL_N_1 DT_INTEL_APL_GPIO_D0C50000_LABEL "_N_1"
#define DT_APL_GPIO_LABEL_N_2 DT_INTEL_APL_GPIO_D0C50000_LABEL "_N_2"
#define DT_APL_GPIO_LABEL_NW_0 DT_INTEL_APL_GPIO_D0C50000_LABEL "_NW_0"
#define DT_APL_GPIO_LABEL_NW_1 DT_INTEL_APL_GPIO_D0C50000_LABEL "_NW_1"
#define DT_APL_GPIO_LABEL_NW_2 DT_INTEL_APL_GPIO_D0C50000_LABEL "_NW_2"
#define DT_APL_GPIO_LABEL_W_0 DT_INTEL_APL_GPIO_D0C50000_LABEL "_W_0"
#define DT_APL_GPIO_LABEL_W_1 DT_INTEL_APL_GPIO_D0C50000_LABEL "_W_1"
#define DT_APL_GPIO_LABEL_SW_0 DT_INTEL_APL_GPIO_D0C50000_LABEL "_SW_0"
#define DT_APL_GPIO_LABEL_SW_1 DT_INTEL_APL_GPIO_D0C50000_LABEL "_SW_1"
soc: apollo_lake: fix build errors for GPIO due to DTS changes The DTS changes introduced in 7ae220c845194a1c68b258cd4f9b1e63df26eb41 changes the naming of GPIO related macros. This updates the usage of previous macros via DTS fixup. Fixes #10993 Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-11-02 01:34:10 +08:00
arch/x86/soc: add SoC configuration for Apollo Lake This adds the SoC configuration for Apollo Lake. This is based on the Atom configuration. Origin: Original Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-07-17 09:37:14 +08:00
/* End of SoC Level DTS fixup file */