41 lines
1.9 KiB
C
41 lines
1.9 KiB
C
/*
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* Copyright (c) 2018-2019 Intel Corporation Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* SoC level DTS fixup file */
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#define DT_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
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#define DT_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS
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#define DT_RAM_SIZE CONFIG_SRAM_SIZE
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#define DT_ROM_SIZE CONFIG_FLASH_SIZE
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#define DT_IOAPIC_BASE_ADDRESS DT_INTEL_IOAPIC_FEC00000_BASE_ADDRESS
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#define DT_APL_GPIO_BASE_ADDRESS_N DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_0
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#define DT_APL_GPIO_BASE_ADDRESS_NW DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_1
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#define DT_APL_GPIO_BASE_ADDRESS_W DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_2
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#define DT_APL_GPIO_BASE_ADDRESS_SW DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_3
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#define DT_APL_GPIO_IRQ DT_INTEL_APL_GPIO_D0C50000_IRQ_0
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#define DT_APL_GPIO_IRQ_PRIORITY DT_INTEL_APL_GPIO_D0C50000_IRQ_0_PRIORITY
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#define DT_APL_GPIO_IRQ_SENSE DT_INTEL_APL_GPIO_D0C50000_IRQ_0_SENSE
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#define DT_APL_GPIO_MEM_SIZE_N DT_INTEL_APL_GPIO_D0C50000_SIZE_0
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#define DT_APL_GPIO_MEM_SIZE_NW DT_INTEL_APL_GPIO_D0C50000_SIZE_1
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#define DT_APL_GPIO_MEM_SIZE_W DT_INTEL_APL_GPIO_D0C50000_SIZE_2
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#define DT_APL_GPIO_MEM_SIZE_SW DT_INTEL_APL_GPIO_D0C50000_SIZE_3
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#define DT_APL_GPIO_LABEL_N_0 DT_INTEL_APL_GPIO_D0C50000_LABEL "_N_0"
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#define DT_APL_GPIO_LABEL_N_1 DT_INTEL_APL_GPIO_D0C50000_LABEL "_N_1"
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#define DT_APL_GPIO_LABEL_N_2 DT_INTEL_APL_GPIO_D0C50000_LABEL "_N_2"
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#define DT_APL_GPIO_LABEL_NW_0 DT_INTEL_APL_GPIO_D0C50000_LABEL "_NW_0"
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#define DT_APL_GPIO_LABEL_NW_1 DT_INTEL_APL_GPIO_D0C50000_LABEL "_NW_1"
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#define DT_APL_GPIO_LABEL_NW_2 DT_INTEL_APL_GPIO_D0C50000_LABEL "_NW_2"
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#define DT_APL_GPIO_LABEL_W_0 DT_INTEL_APL_GPIO_D0C50000_LABEL "_W_0"
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#define DT_APL_GPIO_LABEL_W_1 DT_INTEL_APL_GPIO_D0C50000_LABEL "_W_1"
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#define DT_APL_GPIO_LABEL_SW_0 DT_INTEL_APL_GPIO_D0C50000_LABEL "_SW_0"
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#define DT_APL_GPIO_LABEL_SW_1 DT_INTEL_APL_GPIO_D0C50000_LABEL "_SW_1"
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/* End of SoC Level DTS fixup file */
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