20 lines
531 B
C
20 lines
531 B
C
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/*
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* Copyright (c) 2018 Intel Corporation Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* SoC level DTS fixup file */
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#define CONFIG_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
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#define CONFIG_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS
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#define CONFIG_RAM_SIZE CONFIG_SRAM_SIZE
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#define CONFIG_ROM_SIZE CONFIG_FLASH_SIZE
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#define CONFIG_IOAPIC_BASE_ADDRESS INTEL_IOAPIC_FEC00000_BASE_ADDRESS
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/* End of SoC Level DTS fixup file */
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