OrgZephyr/zephyr
OrgZephyr
/
zephyr
mirror of https://github.com/zephyrproject-rtos/zephyr.git
1
0
Fork 0
Code Issues Releases Wiki Activity
zephyr/soc/neorv32/Kconfig

37 lines
918 B
Plaintext
Raw Normal View History

soc: riscv: privilege: add neorv32 processor suppport Add support for the open-source NEORV32 RISC-V compatible processor system (SoC). Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-08-15 05:52:35 +08:00
# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
# SPDX-License-Identifier: Apache-2.0
soc: riscv: neorv32: reorganize SoC folder Move out of riscv-privileged and convert to a standalone SoC. Note that the family/series structure has been dropped in favor of a single SoC (what NEORV32 seems to be). Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-03 22:50:51 +08:00
config SOC_NEORV32
soc: riscv: privilege: add neorv32 processor suppport Add support for the open-source NEORV32 RISC-V compatible processor system (SoC). Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-08-15 05:52:35 +08:00
select RISCV
riscv: Rework and cleanup Kconfig This patch is doing several things: - Core ISA and extension Kconfig symbols have now a formalized name (CONFIG_RISCV_ISA_* and CONFIG_RISCV_ISA_EXT_*) - a new Kconfig.isa file was introduced with the full set of extensions currently supported by the v2.2 spec - a new Kconfig.core file was introduced to host all the RISCV cores (currently only E31) - ISA and extensions settings are moved to SoC configuration files Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-05-12 18:03:47 +08:00
select RISCV_ISA_RV32I
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_A
riscv: Introduce Zicsr and Zifencei extensions And enable the new extensions on all the SoCs. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-06-13 23:21:35 +08:00
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
arch: riscv: introduce RISCV_PRIVILEGED Introduce a new arch level Kconfig option to signal the implementation of the RISCV Privileged ISA spec. This replaces SOC_FAMILY_RISCV_PRIVILEGED, because this is not a SoC specific property, nor a SoC family. Note that the SoC family naming scheme will be fixed in upcoming commits. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-03 19:39:36 +08:00
select RISCV_PRIVILEGED
arch: riscv: imply XIP config pushed to SoC level 'imply XIP' pushed from arch/Kconfig/'config RISCV' to riscv SoCs Kconfig files to allow riscv SoCs having XIP enabled (or not) at SoC level Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
2024-08-30 04:59:43 +08:00
imply XIP
soc: riscv: neorv32: reorganize SoC folder Move out of riscv-privileged and convert to a standalone SoC. Note that the family/series structure has been dropped in favor of a single SoC (what NEORV32 seems to be). Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-03 22:50:51 +08:00
if SOC_NEORV32
config SOC_NEORV32_V1_8_6
bool "v1.8.6"
# NEORV32 RISC-V ISA A extension implements only LR/SC, not AMO
select ATOMIC_OPERATIONS_C
config SOC_NEORV32_VERSION
hex
default 0x01080600 if SOC_NEORV32_V1_8_6
help
The targeted NEORV32 version as BCD-coded number. The format is
identical to that of the NEORV32 Machine implementation ID (mimpid)
register.
config SOC_NEORV32_ISA_C
bool "RISC-V ISA Extension \"C\""
select RISCV_ISA_EXT_C
help
Enable this if the NEORV32 CPU implementation supports the RISC-V ISA
"C" extension (Compressed Instructions).
endif # SOC_NEORV32