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zephyr/soc/riscv/riscv-privileged/neorv32/Kconfig.series

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soc: riscv: privilege: add neorv32 processor suppport Add support for the open-source NEORV32 RISC-V compatible processor system (SoC). Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-08-15 05:52:35 +08:00
# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_NEORV32
bool "NEORV32 Processor"
select RISCV
riscv: Rework and cleanup Kconfig This patch is doing several things: - Core ISA and extension Kconfig symbols have now a formalized name (CONFIG_RISCV_ISA_* and CONFIG_RISCV_ISA_EXT_*) - a new Kconfig.isa file was introduced with the full set of extensions currently supported by the v2.2 spec - a new Kconfig.core file was introduced to host all the RISCV cores (currently only E31) - ISA and extensions settings are moved to SoC configuration files Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-05-12 18:03:47 +08:00
select RISCV_ISA_RV32I
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_A
riscv: Introduce Zicsr and Zifencei extensions And enable the new extensions on all the SoCs. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-06-13 23:21:35 +08:00
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
arch: riscv: introduce RISCV_PRIVILEGED Introduce a new arch level Kconfig option to signal the implementation of the RISCV Privileged ISA spec. This replaces SOC_FAMILY_RISCV_PRIVILEGED, because this is not a SoC specific property, nor a SoC family. Note that the SoC family naming scheme will be fixed in upcoming commits. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-03 19:39:36 +08:00
select RISCV_PRIVILEGED
soc: riscv: privilege: add neorv32 processor suppport Add support for the open-source NEORV32 RISC-V compatible processor system (SoC). Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-08-15 05:52:35 +08:00
help
Enable support for the NEORV32 Processor (SoC).
The NEORV32 CPU implementation must have the following RISC-V ISA
extensions enabled in order to support Zephyr:
- M (Integer Multiplication and Division)
- Zicsr (Control and Status Register (CSR) Instructions)
The following NEORV32 CPU ISA extensions are not currently supported
by Zephyr and can safely be disabled:
- A (Atomic Instructions)
- E (Embedded, only 16 integer registers)
- Zbb (Basic Bit Manipulation)
- Zfinx (Floating Point in Integer Registers)