22 lines
760 B
Plaintext
22 lines
760 B
Plaintext
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# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_NEORV32
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bool "NEORV32 Processor"
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select RISCV
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select SOC_FAMILY_RISCV_PRIVILEGE
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help
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Enable support for the NEORV32 Processor (SoC).
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The NEORV32 CPU implementation must have the following RISC-V ISA
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extensions enabled in order to support Zephyr:
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- M (Integer Multiplication and Division)
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- Zicsr (Control and Status Register (CSR) Instructions)
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The following NEORV32 CPU ISA extensions are not currently supported
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by Zephyr and can safely be disabled:
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- A (Atomic Instructions)
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- E (Embedded, only 16 integer registers)
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- Zbb (Basic Bit Manipulation)
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- Zfinx (Floating Point in Integer Registers)
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