zephyr/soc/riscv/esp32c3/soc_irq.S

/* Copyright 2021 Espressif Systems (Shanghai) PTE LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <offsets.h>
#include <zephyr/toolchain.h>

/* Exports */
GTEXT(__soc_is_irq)
GTEXT(__soc_handle_irq)
GTEXT(soc_intr_get_next_source)

SECTION_FUNC(exception.other, __soc_is_irq)
	csrr a0, mcause
	srli a0, a0, 31
	ret

SECTION_FUNC(exception.other, __soc_handle_irq)
	addi sp, sp,-4
	sw  ra, 0x00(sp)
	la t1, soc_intr_get_next_source
	jalr ra, t1, 0
	lw  ra, 0x00(sp)
	addi sp, sp, 4
	ret
soc: esp32c3: added initial soc support files for esp32c3 by adding the soc specific files such: soc initialization code, linker scripts and support for esp32c3 devkitm Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com> Signed-off-by: Felipe Neves <felipe.neves@espressif.com> 2021-04-13 06:39:04 +08:00			`/* Copyright 2021 Espressif Systems (Shanghai) PTE LTD`
			`*`
			`* SPDX-License-Identifier: Apache-2.0`
			`*/`

			`#include <offsets.h>`
asm: update files with <zephyr/...> include prefix Assembler files were not migrated with the new <zephyr/...> prefix. Note that the conversion has been scripted, refer to #45388 for more details. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no> 2022-05-09 19:56:13 +08:00			`#include <zephyr/toolchain.h>`
soc: esp32c3: added initial soc support files for esp32c3 by adding the soc specific files such: soc initialization code, linker scripts and support for esp32c3 devkitm Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com> Signed-off-by: Felipe Neves <felipe.neves@espressif.com> 2021-04-13 06:39:04 +08:00
			`/* Exports */`
			`GTEXT(__soc_is_irq)`
			`GTEXT(__soc_handle_irq)`
interrupt_controller: intc_esp32c3: added intc driver For esp32c3 and replaces the hardcoded interrupt attaching procedures with this new driver. Signed-off-by: Felipe Neves <felipe.neves@espressif.com> 2021-08-30 21:04:34 +08:00			`GTEXT(soc_intr_get_next_source)`
soc: esp32c3: added initial soc support files for esp32c3 by adding the soc specific files such: soc initialization code, linker scripts and support for esp32c3 devkitm Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com> Signed-off-by: Felipe Neves <felipe.neves@espressif.com> 2021-04-13 06:39:04 +08:00
			`SECTION_FUNC(exception.other, __soc_is_irq)`
			`csrr a0, mcause`
			`srli a0, a0, 31`
			`ret`

			`SECTION_FUNC(exception.other, __soc_handle_irq)`
interrupt_controller: intc_esp32c3: added intc driver For esp32c3 and replaces the hardcoded interrupt attaching procedures with this new driver. Signed-off-by: Felipe Neves <felipe.neves@espressif.com> 2021-08-30 21:04:34 +08:00			`addi sp, sp,-4`
			`sw ra, 0x00(sp)`
			`la t1, soc_intr_get_next_source`
riscv: fix non-standard assembly of RISC-V Non-standard `jalr rd, rs` pseudo-instructions are used. This commit changes them to `ret` for standard return pseudo-instruction or `jalr rd, rs, 0` for no offset jump register and link. Fixes #41100. Signed-off-by: Henry Hsieh <r901042004@yahoo.com.tw> 2021-12-14 22:46:42 +08:00			`jalr ra, t1, 0`
interrupt_controller: intc_esp32c3: added intc driver For esp32c3 and replaces the hardcoded interrupt attaching procedures with this new driver. Signed-off-by: Felipe Neves <felipe.neves@espressif.com> 2021-08-30 21:04:34 +08:00			`lw ra, 0x00(sp)`
			`addi sp, sp, 4`
soc: esp32c3: added initial soc support files for esp32c3 by adding the soc specific files such: soc initialization code, linker scripts and support for esp32c3 devkitm Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com> Signed-off-by: Felipe Neves <felipe.neves@espressif.com> 2021-04-13 06:39:04 +08:00			`ret`