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zephyr/drivers/interrupt_controller/Kconfig.clic

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drivers: interrupt-controller: add Nuclei ECLIC driver Add support for the ECLIC interrupt controller which is used with the Nuclei processor core. Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2021-11-15 07:34:11 +08:00
# Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
# SPDX-License-Identifier: Apache-2.0
config NUCLEI_ECLIC
bool "Enhanced Core Local Interrupt Controller (ECLIC)"
drivers: intc: Update drivers to use devicetree Kconfig symbol Update intc drivers to use DT_HAS_<compat>_ENABLED Kconfig symbol to expose the driver and enable it by default based on devicetree. We remove 'depend on' Kconfig for symbols that would be implied by the devicetree node existing. Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-22 14:46:51 +08:00
default y
depends on DT_HAS_NUCLEI_ECLIC_ENABLED
drivers: interrupt_controller: nuclei_eclic: always use clic common entry When CONFIG_RISCV_VECTORED_MODE is disabled, CLIC claims interrupts using CSR 'mnxti' and handles all pending interrupts before exiting the ISR. When CONFIG_RISCV_VECTORED_MODE is enabled, all interrupts use vector mode and are claimed automatically. The RISC-V common ISR is used for interrupts hooked into SW ISR table, but it only handle one pending interrupt per ISR. This commit enhances CLIC to set vector mode for direct ISRs only and use the CLIC common entry for regular ISRs to handles multiple pending interrupts in an ISR. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2024-08-05 11:17:39 +08:00
select RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING
drivers: interrupt_controller: nuclei_eclic: support vector mode setting Implement riscv_clic_irq_vector_set() for Nuclei CLIC driver. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2024-08-06 11:31:24 +08:00
select CLIC_SMCLICSHV_EXT if RISCV_VECTORED_MODE
drivers: interrupt-controller: add Nuclei ECLIC driver Add support for the ECLIC interrupt controller which is used with the Nuclei processor core. Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2021-11-15 07:34:11 +08:00
help
Interrupt controller for Nuclei SoC core.
riscv: irq: Set selective hardware vectoring The mechanism for hardware vectoring has changed in the clic spec (https://github.com/riscv/riscv-fast-interrupt) in 2019. Before vectoring was enabled via `mode` bits in `mtvec`. Support for this was added in fc480c9382a218130eaf7308cbbad7194c71b414. With more current clic implementations, this does not work anymore. Changing the `mode` bits is reserved. Vectoring can be enabled individually in the `shv` bit of `clicintattr[i]`. Since the old mechanism is still used, I added a new Kconfig for it. If this Kconfig is not set, we use the `shv` bit for harware vectoring. Signed-off-by: Greter Raffael <rgreter@baumer.com>
2023-12-21 20:41:59 +08:00
drivers: interrupt_controller: add intc_nrfx_clic Add interrupt controller driver for Nordic Semiconductor VPR CLIC. Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
2024-04-04 17:08:44 +08:00
config NRFX_CLIC
bool "VPR Core Local Interrpt Controller (CLIC)"
default y
depends on DT_HAS_NORDIC_NRF_CLIC_ENABLED
drivers: intc: VPR CLIC should make sure GEN_IRQ_VECTOR_TABLE is enabled VPR cores CLIC supports vectored mode only. Select `GEN_IRQ_VECTOR_TABLE` such that it can't be disabled. Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2024-05-21 21:01:40 +08:00
select GEN_IRQ_VECTOR_TABLE
drivers: interrupt_controller: add intc_nrfx_clic Add interrupt controller driver for Nordic Semiconductor VPR CLIC. Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
2024-04-04 17:08:44 +08:00
help
Interrupt controller for Nordic VPR cores.
soc: common: riscv-privileged: add riscv_clic_irq_vector_set() for clic Introduce riscv_clic_irq_vector_set() to implement z_riscv_irq_vector_set() for CLIC. This commit also introduces CONFIG_CLIC_SMCLICSHV_EXT to indicate support for the smclicshv extenion and riscv_clic_irq_vector_set(). Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2024-08-05 10:41:59 +08:00
config CLIC_SMCLICSHV_EXT
bool
help
The selective hardware vectoring extension gives users the flexibility
to select the behavior for each interrupt. The CLIC driver needs to
implement the riscv_clic_irq_vector_set() function.
drivers: interrupt_controller: add intc_nrfx_clic Add interrupt controller driver for Nordic Semiconductor VPR CLIC. Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
2024-04-04 17:08:44 +08:00
if NUCLEI_ECLIC
riscv: irq: Set selective hardware vectoring The mechanism for hardware vectoring has changed in the clic spec (https://github.com/riscv/riscv-fast-interrupt) in 2019. Before vectoring was enabled via `mode` bits in `mtvec`. Support for this was added in fc480c9382a218130eaf7308cbbad7194c71b414. With more current clic implementations, this does not work anymore. Changing the `mode` bits is reserved. Vectoring can be enabled individually in the `shv` bit of `clicintattr[i]`. Since the old mechanism is still used, I added a new Kconfig for it. If this Kconfig is not set, we use the `shv` bit for harware vectoring. Signed-off-by: Greter Raffael <rgreter@baumer.com>
2023-12-21 20:41:59 +08:00
config LEGACY_CLIC
bool "Use the legacy clic specification"
depends on RISCV_HAS_CLIC
help
Enables legacy clic, where smclicshv extension is not supported and
hardware vectoring is set via mode bits of mtvec.
drivers: interrupt_controller: add intc_nrfx_clic Add interrupt controller driver for Nordic Semiconductor VPR CLIC. Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
2024-04-04 17:08:44 +08:00
endif # NUCLEI_ECLIC