When CONFIG_RISCV_VECTORED_MODE is disabled, CLIC claims interrupts using
CSR 'mnxti' and handles all pending interrupts before exiting the ISR.
When CONFIG_RISCV_VECTORED_MODE is enabled, all interrupts use vector mode
and are claimed automatically. The RISC-V common ISR is used for interrupts
hooked into SW ISR table, but it only handle one pending interrupt per ISR.
This commit enhances CLIC to set vector mode for direct ISRs only and use
the CLIC common entry for regular ISRs to handles multiple pending
interrupts in an ISR.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Introduce riscv_clic_irq_vector_set() to implement z_riscv_irq_vector_set()
for CLIC. This commit also introduces CONFIG_CLIC_SMCLICSHV_EXT to indicate
support for the smclicshv extenion and riscv_clic_irq_vector_set().
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
CLIC should be the first level interrupt controller because it replaces
the basic RISC-V local interrupt.
The interrupt level in CLIC controls preemption between IRQs, rather than
specifying the number of nested interrupt controllers.
Removed CONFIG_MULTI_LEVEL_INTERRUPTS and the incorrect interrupt level.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
VPR cores CLIC supports vectored mode only. Select
`GEN_IRQ_VECTOR_TABLE` such that it can't be disabled.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
According to the clic specification
(https://github.com/riscv/riscv-fast-interrupt), the mnxti register has
be written, in order to clear the pending bit for non-vectored
interrupts. For vectored interrupts, this is automatically done.
From the spec:
"If the pending interrupt is edge-triggered, hardware will automatically
clear the corresponding pending bit when the CSR instruction that
accesses xnxti includes a write."
I added a kconfig `RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING` to allow custom
irq handling. If enabled, `__soc_handle_all_irqs` has to be implemented.
For clic, non-vectored mode, I added a `__soc_handle_all_irqs`, that
handles the pending interrupts according to the pseudo code in the spec.
Signed-off-by: Greter Raffael <rgreter@baumer.com>
The mechanism for hardware vectoring has changed in the clic spec
(https://github.com/riscv/riscv-fast-interrupt) in 2019. Before
vectoring was enabled via `mode` bits in `mtvec`. Support for this was
added in fc480c9382.
With more current clic implementations, this does not work anymore.
Changing the `mode` bits is reserved. Vectoring can be enabled
individually in the `shv` bit of `clicintattr[i]`.
Since the old mechanism is still used, I added a new Kconfig for it.
If this Kconfig is not set, we use the `shv` bit for harware vectoring.
Signed-off-by: Greter Raffael <rgreter@baumer.com>
Multilevel interrupt configs are leaking into every single build without
this option being enabled, so guard the Kconfig and include files to
avoid this.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Update intc drivers to use DT_HAS_<compat>_ENABLED Kconfig symbol
to expose the driver and enable it by default based on devicetree.
We remove 'depend on' Kconfig for symbols that would be implied by
the devicetree node existing.
Signed-off-by: Kumar Gala <galak@kernel.org>
Introduce a new RISCV_HAS_CLIC symbol for platforms using CLIC,
reorganize the Kconfigs and make the Nuclei ECLIC depending on the new
symbol.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Jimmy Zheng