soc: common: riscv-privileged: add riscv_clic_irq_vector_set() for clic

Introduce riscv_clic_irq_vector_set() to implement z_riscv_irq_vector_set()
for CLIC. This commit also introduces CONFIG_CLIC_SMCLICSHV_EXT to indicate
support for the smclicshv extenion and riscv_clic_irq_vector_set().

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>

drivers/interrupt_controller/Kconfig.clic

@@ -17,6 +17,13 @@ config NRFX_CLIC
 	help
 	  Interrupt controller for Nordic VPR cores.
 
+config CLIC_SMCLICSHV_EXT
+	bool
+	help
+	  The selective hardware vectoring extension gives users the flexibility
+	  to select the behavior for each interrupt. The CLIC driver needs to
+	  implement the riscv_clic_irq_vector_set() function.
+
 if NUCLEI_ECLIC
 
 config LEGACY_CLIC

include/zephyr/drivers/interrupt_controller/riscv_clic.h

@@ -43,4 +43,11 @@ int riscv_clic_irq_is_enabled(uint32_t irq);
  */
 void riscv_clic_irq_priority_set(uint32_t irq, uint32_t prio, uint32_t flags);
 
+/**
+ * @brief Set vector mode of interrupt
+ *
+ * @param irq interrupt ID
+ */
+void riscv_clic_irq_vector_set(uint32_t irq);
+
 #endif /* ZEPHYR_INCLUDE_DRIVERS_RISCV_CLIC_H_ */

soc/common/riscv-privileged/soc_common_irq.c

@@ -37,6 +37,15 @@ void z_riscv_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flag
 	riscv_clic_irq_priority_set(irq, prio, flags);
 }
 
+void z_riscv_irq_vector_set(unsigned int irq)
+{
+#if defined(CONFIG_CLIC_SMCLICSHV_EXT)
+	riscv_clic_irq_vector_set(irq);
+#else
+	ARG_UNUSED(irq);
+#endif
+}
+
 #else /* PLIC + HLINT/CLINT or HLINT/CLINT only */
 
 void arch_irq_enable(unsigned int irq)