2019-04-29 21:39:56 +08:00
|
|
|
/**
|
|
|
|
******************************************************************************
|
|
|
|
* @file FatFs/FatFs_MultiDrives/Src/main.c
|
|
|
|
* @author MCD Application Team
|
|
|
|
* @brief Main program body
|
|
|
|
* This sample code shows how to use FatFs with multi drives.
|
|
|
|
******************************************************************************
|
|
|
|
* @attention
|
|
|
|
*
|
2021-12-14 16:25:05 +08:00
|
|
|
* Copyright (c) 2016 STMicroelectronics.
|
|
|
|
* All rights reserved.
|
2019-04-29 21:39:56 +08:00
|
|
|
*
|
2021-12-14 16:25:05 +08:00
|
|
|
* This software is licensed under terms that can be found in the LICENSE file
|
|
|
|
* in the root directory of this software component.
|
|
|
|
* If no LICENSE file comes with this software, it is provided AS-IS.
|
2019-04-29 21:39:56 +08:00
|
|
|
*
|
|
|
|
******************************************************************************
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* Includes ------------------------------------------------------------------*/
|
|
|
|
#include "main.h"
|
|
|
|
|
|
|
|
/* Private typedef -----------------------------------------------------------*/
|
|
|
|
/* Private define ------------------------------------------------------------*/
|
|
|
|
/* Private macro -------------------------------------------------------------*/
|
|
|
|
/* Private variables ---------------------------------------------------------*/
|
|
|
|
FATFS RAMFatFs, SDFatFs; /* File system objects logical drives */
|
|
|
|
FIL RAMFile, SDFile; /* File objects */
|
|
|
|
char RAMpath[4], SDpath[4]; /* RAM disk and SD card logical drives paths */
|
|
|
|
uint8_t workBuffer[2*_MAX_SS];
|
|
|
|
|
|
|
|
/* Private function prototypes -----------------------------------------------*/
|
2021-12-14 16:25:05 +08:00
|
|
|
static void MPU_Config(void);
|
2019-04-29 21:39:56 +08:00
|
|
|
static void SystemClock_Config(void);
|
|
|
|
static void Error_Handler(void);
|
|
|
|
static void CPU_CACHE_Enable(void);
|
|
|
|
|
|
|
|
/* Private functions ---------------------------------------------------------*/
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief Main program
|
|
|
|
* @param None
|
|
|
|
* @retval None
|
|
|
|
*/
|
|
|
|
int main(void)
|
|
|
|
{
|
|
|
|
FRESULT res1, res2; /* FatFs function common result codes */
|
|
|
|
uint32_t byteswritten1, byteswritten2; /* File write counts */
|
|
|
|
uint32_t bytesread1, bytesread2; /* File read counts */
|
|
|
|
uint8_t wtext[] = "This is STM32 working with FatFs"; /* File write buffer */
|
|
|
|
uint8_t rtext1[100], rtext2[100]; /* File read buffers */
|
|
|
|
|
2021-12-14 16:25:05 +08:00
|
|
|
/* Configure the MPU attributes */
|
|
|
|
MPU_Config();
|
|
|
|
|
2019-04-29 21:39:56 +08:00
|
|
|
/* Enable the CPU Cache */
|
|
|
|
CPU_CACHE_Enable();
|
|
|
|
|
|
|
|
/* STM32F7xx HAL library initialization:
|
|
|
|
- Configure the Flash ART accelerator on ITCM interface
|
|
|
|
- Configure the Systick to generate an interrupt each 1 msec
|
|
|
|
- Set NVIC Group Priority to 4
|
|
|
|
- Global MSP (MCU Support Package) initialization
|
|
|
|
*/
|
|
|
|
HAL_Init();
|
|
|
|
|
|
|
|
/* Configure the system clock to 216 MHz */
|
|
|
|
SystemClock_Config();
|
|
|
|
|
|
|
|
/* Configure LED1 and LED3 */
|
|
|
|
BSP_LED_Init(LED1);
|
|
|
|
BSP_LED_Init(LED3);
|
|
|
|
|
|
|
|
/*##-1- Link the disk I/O drivers ##########################################*/
|
|
|
|
if((FATFS_LinkDriver(&SDRAMDISK_Driver, RAMpath) == 0) && (FATFS_LinkDriver(&SD_Driver, SDpath) == 0))
|
|
|
|
{
|
|
|
|
/*##-2- Register the file system object to the FatFs module ##############*/
|
|
|
|
res1 = f_mount(&RAMFatFs, (TCHAR const*)RAMpath, 0);
|
|
|
|
res2 = f_mount(&SDFatFs, (TCHAR const*)SDpath, 0);
|
|
|
|
|
|
|
|
if((res1 != FR_OK) || (res2 != FR_OK))
|
|
|
|
{
|
|
|
|
/* FatFs Initialization Error */
|
|
|
|
Error_Handler();
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/*##-3- Create a FAT file system (format) on the logical drives ########*/
|
|
|
|
/* WARNING: Formatting the uSD card will delete all content on the device */
|
|
|
|
res1 = f_mkfs((TCHAR const*)RAMpath, FM_ANY, 0, workBuffer, sizeof(workBuffer));
|
|
|
|
res2 = f_mkfs((TCHAR const*)SDpath, FM_ANY, 0, workBuffer, sizeof(workBuffer));
|
|
|
|
|
|
|
|
if((res1 != FR_OK) || (res2 != FR_OK))
|
|
|
|
{
|
|
|
|
/* FatFs Format Error */
|
|
|
|
Error_Handler();
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/*##-4- Create and Open new text file objects with write access ######*/
|
|
|
|
res1 = f_open(&RAMFile, "0:STM32.TXT", FA_CREATE_ALWAYS | FA_WRITE);
|
|
|
|
res2 = f_open(&SDFile, "1:STM32.TXT", FA_CREATE_ALWAYS | FA_WRITE);
|
|
|
|
|
|
|
|
if((res1 != FR_OK) || (res2 != FR_OK))
|
|
|
|
{
|
|
|
|
/* 'STM32.TXT' file Open for write Error */
|
|
|
|
Error_Handler();
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/*##-5- Write data to the text files ###############################*/
|
|
|
|
res1 = f_write(&RAMFile, wtext, sizeof(wtext), (void *)&byteswritten1);
|
|
|
|
res2 = f_write(&SDFile, wtext, sizeof(wtext), (void *)&byteswritten2);
|
|
|
|
|
|
|
|
if((byteswritten1 == 0) || (byteswritten2 == 0) || (res1 != FR_OK) || (res2 != FR_OK))
|
|
|
|
{
|
|
|
|
/* 'STM32.TXT' file write Error */
|
|
|
|
Error_Handler();
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/*##-6- Close the open text files ################################*/
|
|
|
|
f_close(&RAMFile);
|
|
|
|
f_close(&SDFile);
|
|
|
|
|
|
|
|
/*##-7- Open the text files object with read access ##############*/
|
|
|
|
res1 = f_open(&RAMFile, "0:STM32.TXT", FA_READ);
|
|
|
|
res2 = f_open(&SDFile, "1:STM32.TXT", FA_READ);
|
|
|
|
|
|
|
|
if((res1 != FR_OK) || (res2 != FR_OK))
|
|
|
|
{
|
|
|
|
/* 'STM32.TXT' file Open for read Error */
|
|
|
|
Error_Handler();
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/*##-8- Read data from the text files ##########################*/
|
|
|
|
res1 = f_read(&RAMFile, rtext1, sizeof(rtext1), (UINT*)&bytesread1);
|
|
|
|
res2 = f_read(&SDFile, rtext2, sizeof(rtext2), (UINT*)&bytesread2);
|
|
|
|
|
|
|
|
if((res1 != FR_OK) || (res2 != FR_OK))
|
|
|
|
{
|
|
|
|
/* 'STM32.TXT' file Read or EOF Error */
|
|
|
|
Error_Handler();
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/*##-9- Close the open text files ############################*/
|
|
|
|
f_close(&RAMFile);
|
|
|
|
f_close(&SDFile);
|
|
|
|
|
|
|
|
/*##-10- Compare read data with the expected data ############*/
|
|
|
|
if((bytesread1 != byteswritten1) || (bytesread2 != byteswritten2))
|
|
|
|
{
|
|
|
|
/* Read data is different from the expected data */
|
|
|
|
Error_Handler();
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* Success of the demo: no error occurrence */
|
|
|
|
BSP_LED_On(LED1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*##-11- Unlink the disk I/O drivers #######################################*/
|
|
|
|
FATFS_UnLinkDriver(RAMpath);
|
|
|
|
FATFS_UnLinkDriver(SDpath);
|
|
|
|
|
|
|
|
/* Infinite loop */
|
|
|
|
while (1)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief System Clock Configuration
|
|
|
|
* The system Clock is configured as follow :
|
|
|
|
* System Clock source = PLL (HSE)
|
|
|
|
* SYSCLK(Hz) = 216000000
|
|
|
|
* HCLK(Hz) = 216000000
|
|
|
|
* AHB Prescaler = 1
|
|
|
|
* APB1 Prescaler = 4
|
|
|
|
* APB2 Prescaler = 2
|
|
|
|
* HSE Frequency(Hz) = 25000000
|
|
|
|
* PLL_M = 25
|
|
|
|
* PLL_N = 432
|
|
|
|
* PLL_P = 2
|
|
|
|
* PLL_Q = 9
|
|
|
|
* VDD(V) = 3.3
|
|
|
|
* Main regulator output voltage = Scale1 mode
|
|
|
|
* Flash Latency(WS) = 7
|
|
|
|
* @param None
|
|
|
|
* @retval None
|
|
|
|
*/
|
|
|
|
static void SystemClock_Config(void)
|
|
|
|
{
|
|
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct;
|
|
|
|
RCC_OscInitTypeDef RCC_OscInitStruct;
|
|
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
|
|
|
|
|
|
/* Enable HSE Oscillator and activate PLL with HSE as source */
|
|
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
|
|
|
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
|
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
|
|
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
|
|
|
RCC_OscInitStruct.PLL.PLLM = 25;
|
|
|
|
RCC_OscInitStruct.PLL.PLLN = 432;
|
|
|
|
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
|
|
|
|
RCC_OscInitStruct.PLL.PLLQ = 9;
|
|
|
|
RCC_OscInitStruct.PLL.PLLR = 7;
|
|
|
|
|
|
|
|
ret = HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
|
|
|
if(ret != HAL_OK)
|
|
|
|
{
|
|
|
|
while(1) { ; }
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Activate the OverDrive to reach the 216 MHz Frequency */
|
|
|
|
ret = HAL_PWREx_EnableOverDrive();
|
|
|
|
if(ret != HAL_OK)
|
|
|
|
{
|
|
|
|
while(1) { ; }
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
|
|
|
|
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
|
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
|
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
|
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
|
|
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
|
|
|
|
|
|
|
|
ret = HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7);
|
|
|
|
if(ret != HAL_OK)
|
|
|
|
{
|
|
|
|
while(1) { ; }
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief This function is executed in case of error occurrence.
|
|
|
|
* @param None
|
|
|
|
* @retval None
|
|
|
|
*/
|
|
|
|
static void Error_Handler(void)
|
|
|
|
{
|
|
|
|
/* Turn LED3 on */
|
|
|
|
BSP_LED_On(LED3);
|
|
|
|
while(1)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-12-14 16:25:05 +08:00
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief Configure the MPU attributes
|
|
|
|
* @param None
|
|
|
|
* @retval None
|
|
|
|
*/
|
|
|
|
static void MPU_Config(void)
|
|
|
|
{
|
|
|
|
MPU_Region_InitTypeDef MPU_InitStruct;
|
|
|
|
|
|
|
|
/* Disable the MPU */
|
|
|
|
HAL_MPU_Disable();
|
|
|
|
|
|
|
|
/* Configure the MPU as Strongly ordered for not defined regions */
|
|
|
|
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
|
|
|
|
MPU_InitStruct.BaseAddress = 0x00;
|
|
|
|
MPU_InitStruct.Size = MPU_REGION_SIZE_4GB;
|
|
|
|
MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS;
|
|
|
|
MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
|
|
|
|
MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
|
|
|
|
MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
|
|
|
|
MPU_InitStruct.Number = MPU_REGION_NUMBER0;
|
|
|
|
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
|
|
|
|
MPU_InitStruct.SubRegionDisable = 0x87;
|
|
|
|
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
|
|
|
|
|
|
|
|
HAL_MPU_ConfigRegion(&MPU_InitStruct);
|
|
|
|
|
|
|
|
/* Configure the MPU attributes as WT for SDRAM */
|
|
|
|
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
|
|
|
|
MPU_InitStruct.BaseAddress = 0xC0000000;
|
|
|
|
MPU_InitStruct.Size = MPU_REGION_SIZE_32MB;
|
|
|
|
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
|
|
|
|
MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
|
|
|
|
MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
|
|
|
|
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
|
|
|
|
MPU_InitStruct.Number = MPU_REGION_NUMBER1;
|
|
|
|
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
|
|
|
|
MPU_InitStruct.SubRegionDisable = 0x00;
|
|
|
|
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
|
|
|
|
|
|
|
|
HAL_MPU_ConfigRegion(&MPU_InitStruct);
|
|
|
|
|
|
|
|
/* Configure the MPU attributes FMC control registers */
|
|
|
|
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
|
|
|
|
MPU_InitStruct.BaseAddress = 0xA0000000;
|
|
|
|
MPU_InitStruct.Size = MPU_REGION_SIZE_8KB;
|
|
|
|
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
|
|
|
|
MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
|
|
|
|
MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
|
|
|
|
MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
|
|
|
|
MPU_InitStruct.Number = MPU_REGION_NUMBER2;
|
|
|
|
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
|
|
|
|
MPU_InitStruct.SubRegionDisable = 0x0;
|
|
|
|
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
|
|
|
|
|
|
|
|
HAL_MPU_ConfigRegion(&MPU_InitStruct);
|
|
|
|
|
|
|
|
/* Enable the MPU */
|
|
|
|
HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
|
|
|
|
}
|
|
|
|
|
2019-04-29 21:39:56 +08:00
|
|
|
#ifdef USE_FULL_ASSERT
|
|
|
|
/**
|
|
|
|
* @brief Reports the name of the source file and the source line number
|
|
|
|
* where the assert_param error has occurred.
|
|
|
|
* @param file: pointer to the source file name
|
|
|
|
* @param line: assert_param error line source number
|
|
|
|
* @retval None
|
|
|
|
*/
|
|
|
|
void assert_failed(uint8_t* file, uint32_t line)
|
|
|
|
{
|
|
|
|
/* User can add his own implementation to report the file name and line number,
|
|
|
|
ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
|
|
|
|
|
|
|
|
/* Infinite loop */
|
|
|
|
while (1)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief CPU L1-Cache enable.
|
|
|
|
* @param None
|
|
|
|
* @retval None
|
|
|
|
*/
|
|
|
|
static void CPU_CACHE_Enable(void)
|
|
|
|
{
|
|
|
|
/* Enable I-Cache */
|
|
|
|
SCB_EnableICache();
|
|
|
|
|
|
|
|
/* Enable D-Cache */
|
|
|
|
SCB_EnableDCache();
|
|
|
|
}
|
|
|
|
|