When setting the sample rate (`es8311_setsamplerate`) and the bits
per sample (`es8311_setbitspersample`), check their return value in
`es8311_configure`. Also, this commit ensures that these functions
are called after `es8311_reset` to avoid these values to be set to
the default values.
The ESP32-S3-Korvo-2 is a multimedia development board based on the
ESP32-S3 chip. It is equipped with a two-microphone array which is
suitable for voice recognition and near/far-field voice wake-up
applications. The board integrates multiple peripherals such as
LCD, camera, and microSD card. It also supports JPEG video stream
processing. With all of its outstanding features, the board is an
ideal choice for the development of low-cost and low-power
network-connected audio and video products.
Other ESP32-S3 modules (with embedded flash and PSRAM) were added.
Also, the `help` section of the Kconfig was updated to better
describe the modules' flash and PSRAM sizes.
Steppoint can be implemented by icount(instruction count)
from RISC-V debug extension, but it may not implemented in all RISC-V cores.
Unfortunately, the currently supported RISC-V cores do not implement it.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
According to the POSIX standard, `fstat` and `stat` should return 0
(`OK`) on success. This commit changed the underlying `spiffs`
implementation to follow the POSIX standard.
Provide `up_copy_section` function that enables copying data using
the data bus. If the memory destination address is accessible
through the instruction bus, the data is copied using the
correspondent address accessible through the data bus.
The ELF loader needs to load the app into the memory before
executing it from the same location. As expected, this memory space
should be able to execute code. For architectures containing data
and instruction buses, the instruction bus may not be able to be
accessed in a non-aligned way, which is usually required when
copying data to that location. Eventually, this same memory space
can be accessed through the data bus, using different address
ranges. This commit enables accessing the memory through the data
bus to copy the app's data before executing it when
`CONFIG_ARCH_HAVE_TEXT_HEAP_WORD_ALIGNED_READ` is enabled.
rename _rdtsc macro to rdtsc to avoid conflict with external code
rename rdtsc macro to rdtscp to be the same as asm instruction used
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
The buffer initialization function (`i2s_buf_initialize`) calls
`i2s_buf_free`, which performs buffer initialization within a
critical section (`spin_lock_irqsave`). If this function is called
under the same critical section (same spinlock), initialization
will hang.
Check if only one driver is used as console to avoid a non-working console
because a different one is selected and has higher priority than the one we wanted
This change implements a driver for the two watchdog timers on the BL808, and enables it as part of the timer config. The driver is based on the GP timer driver.
arch/xtensa: add support for capture driver on ESP32 and ESP32|S3|
Squashed:
Initial settings for MCPWM Capture on board level
Created lower half files - compilation ok
Using capture debug features. Simple example on fops works
Successful duty and freq calculation
Documentation update
Fixed and added interupt capabilities for all 3 capture channels
Cleaned defconfig
Renamed macros, added S3 options and moved arch source to common dir
Added support for ESP32S3
Added capture example to defconfig and renamed
Basic bring up ready. New Kconfig options for motor.
Good motor registration
Working on enabling pwm generators
Working on enabling pwm generators
Added fops functions
Success on PWM 50%
stable pwm operation for bdc
Added loopback option for testing
Improved rules on fsm
Working motor direction control
Testing new ISR for fault handling
Issues on fault ISR
Removed fault implementation (not working)
Added support for esp32s3
Documentation improvements
Added default motor spin direction
Added parameter change while running
Review fixes
arch/xtensa: add support for fault signal on motor control
Squashed:
Initial settings for MCPWM Capture on board level
Created lower half files - compilation ok
Using capture debug features. Simple example on fops works
Successful duty and freq calculation
Documentation update
Fixed and added interupt capabilities for all 3 capture channels
Cleaned defconfig
Renamed macros, added S3 options and moved arch source to common dir
Added support for ESP32S3
Added capture example to defconfig and renamed
Basic bring up ready. New Kconfig options for motor.
Good motor registration
Working on enabling pwm generators
Working on enabling pwm generators
Added fops functions
Success on PWM 50%
stable pwm operation for bdc
Added loopback option for testing
Improved rules on fsm
Working motor direction control
Testing new ISR for fault handling
Issues on fault ISR
Removed fault implementation (not working)
Added support for esp32s3
Documentation improvements
Added default motor spin direction
Added parameter change while running
Got responsive fault indicator
Working brakes - still need to work on starting isr
Fixed single-time ISR initializiation
Working soft brake on fault
Improved KConfig for BDC and BLDC
Kconfig fixed at board level
nucleo-f4229zi board does not come with external ram.
Looking at netnsh config, these changes are also not present.
Issue found when registering i2c char driver for i2ctool. zalloc
returned -ENOMEM
Tiago Medicci