Commit Graph

56135 Commits

Author SHA1 Message Date
xuxingliang 9af5fc5d09 fs/shm: alloc aligned memory if CPU has cache
For kernel builds, shared memory is automatically aligned to page size.
For flat and protected builds, we align the memory size to the CPU cache
line size.

Failure to align memory properly could result in partial data read/write
by the CPU and peripherals, potentially causing data corruption during
cache flushes or invalidations.

Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
2024-10-27 10:38:58 +08:00
xuxingliang 22bcb88687 fs_heap: add memalign interface
So the share memory can use it to malloc aligned memory.
Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
2024-10-27 10:38:58 +08:00
Xiang Xiao 32784b0898 libc: Refine the arc4random_buf implementation
fill the buffer with getrandom instead random pool
and move the implementation to from crypto to libc

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2024-10-26 18:04:21 -03:00
raiden00pl b5e5cdd851 arch/arm/stm32h7: add workaround for Renode
Add an option to disable busy wait PWR_CSR1_ACTVOSRDY during boot
which doesn't work with Renode simulation
2024-10-26 20:49:49 +08:00
raiden00pl 8b9337fb52 Documentation: add some notes about running NuttX on Renode
add some notes about running NuttX on Renode
2024-10-26 19:37:10 +08:00
chao an 73c032d594 tools/nxstyle: add phy62xx/uart.c into style white list
To skip the style issue:
arch/arm/src/phy62xx/uart.c:59:15: error: Mixed case identifier found
arch/arm/src/phy62xx/uart.c:64:2: error: Mixed case identifier found
arch/arm/src/phy62xx/uart.c:65:2: error: Mixed case identifier found
arch/arm/src/phy62xx/uart.c:70:2: error: Mixed case identifier found
arch/arm/src/phy62xx/uart.c:71:2: error: Mixed case identifier found
arch/arm/src/phy62xx/uart.c:75:2: error: Mixed case identifier found
arch/arm/src/phy62xx/uart.c:77:7: error: Mixed case identifier found

Signed-off-by: chao an <anchao@lixiang.com>
2024-10-26 13:21:29 +08:00
chao an c6591c0f49 driver/serial: remove return value of up_putc()
modify the prototype of up_putc(): remove the return value

The architecture code does not care about the return value of up_putc(), so removing it saves two statements:

Before:                                                    After:
de4c: e52de004  push  {lr}    @ (str lr, [sp, #-4]!)    |  de4c: e52de004  push  {lr}    @ (str lr, [sp, #-4]!)
de50: e24dd014  sub sp, sp, #20                         |  de50: e24dd014  sub sp, sp, #20
de54: e58d0004  str r0, [sp, #4]                        |  de54: e58d0004  str r0, [sp, #4]
de58: e30030f8  movw  r3, #248  @ 0xf8                  |  de58: e30030f8  movw  r3, #248  @ 0xf8
de5c: e3423000  movt  r3, #8192 @ 0x2000                |  de5c: e3423000  movt  r3, #8192 @ 0x2000
de60: e58d300c  str r3, [sp, #12]                       |  de60: e58d300c  str r3, [sp, #12]
de64: e59d1004  ldr r1, [sp, #4]                        |  de64: e59d1004  ldr r1, [sp, #4]
de68: e59d000c  ldr r0, [sp, #12]                       |  de68: e59d000c  ldr r0, [sp, #12]
de6c: ebfffe66  bl  d80c <pl011_putc>                   |  de6c: ebfffe66  bl  d80c <pl011_putc>
de70: e59d3004  ldr r3, [sp, #4]                        |  de70: e28dd014  add sp, sp, #20
de74: e1a00003  mov r0, r3                              |  de74: e49df004  pop {pc}    @ (ldr pc, [sp], #4)
de78: e28dd014  add sp, sp, #20                         |
de7c: e49df004  pop {pc}    @ (ldr pc, [sp], #4)        |

Signed-off-by: chao an <anchao@lixiang.com>
2024-10-26 13:21:29 +08:00
Haiyue Wang d0f957ae85 qemu-intel64: Fixes the linker 'noexecstack' warning
Fix the linker warning based on these two commits:

 ld: warning: fork.o: missing .note.GNU-stack section implies executable stack
 ld: NOTE: This behaviour is deprecated and will be removed in a future version of the linker

commit 36ac812114 ("sim: Fixes the following linker warning:"),
commit b5d640acc5 ("fix Cygwin/MSYS2  ld: unrecognized option '-z'")
2024-10-26 11:10:43 +08:00
raiden00pl da1ff4cf77 arch/arm/stm32: convert error to warning when CCM is not enabled
User may set CONFIG_MM_REGIONS=1 on purpose to disable CCM.
This is a completely normal system config and should not be treated as error.

I found this problem trying to run Renode with stm32f4discovery/nsh but
Renode doesn't support CCM so we have to disable it
2024-10-26 11:02:19 +08:00
chao an 052ea5b20d mm/kasan: extern kasan API only MM_KASAN is enabled
this PR will fix g_region_init is incorrectly linked to the image if MM_KASAN is not enabled.

Signed-off-by: chao an <anchao@lixiang.com>
2024-10-25 19:04:14 +08:00
YAMAMOTO Takashi 6a2e21dd07 esp32: Fix a heap corruption bug with SPIRAM
Don't add SPIRAM ("HEAP2") to both of kernel/user heaps.

Sync with the corresponding logic in esp32s3.
2024-10-25 19:03:22 +08:00
chao an b28f87e3f0 arm/gicv3: replace this_cpu() to up_cpu_index()
If the core id needs to be included in the hardware register
calculation, up_cpu_index() should be used instead of this_cpu().

Signed-off-by: chao an <anchao@lixiang.com>
2024-10-25 14:27:34 +08:00
chao an 9c97f7adaa sched/cpuload: move g_cpuload_wdog to private chapter
coding style

Signed-off-by: chao an <anchao@lixiang.com>
2024-10-25 13:28:51 +08:00
Jinliang Li 5fb0c44f38 arm/armv8-r: optimize generic timer initialization
1. Enable timer and irq finally to make sure timer callback was already
   registered. When the CPU resets, the values of some generic timer
   registers are undefined. Enabling the timer interrupt in advance may
   cause the timer to trigger early while the timer callback is not yet
   registered. This results in the timer ISR being executed, which masks
   the timer interrupt. Since the timer callback is not registered at
   this point, the timer interrupt is not unmasked, further causing the
   system scheduler to hang.
2. Remove timer mask for one-shot timer and that's in isr,
   irq/fiq is disabled. Masking generic timer is not necessary, and it
   may introduce risks, otherwise, mask/unmask must be pair in all
   situations.

Signed-off-by: Jinliang Li <lijinliang1@lixiang.com>
2024-10-25 13:17:08 +08:00
Jinliang Li 40bbe7f3e9 arm/armv8-r: init HSCTLR and HACTLR for EL2
1. init HSCTLR to enable i-cache/d-cache for EL2
2. init HACTLR to enable all access to implementation defined
   registers for EL1.
3. add dsb/isb before switch to EL1 from EL2

Signed-off-by: Jinliang Li <lijinliang1@lixiang.com>
2024-10-25 12:09:47 +08:00
chao an ea4c4ef36a arm/armv8-r: fix unable to switch context in ISR context
Regression by:
| commit 35c8c80a00
| Author: ligd <liguiding1@xiaomi.com>
| Date:   Fri Jul 26 23:14:13 2024 +0800
|
| arch: change nxsched_suspend/resume_scheduler() called position

Signed-off-by: chao an <anchao@lixiang.com>
2024-10-25 09:47:37 +08:00
Tim Hardisty 517c66daf8 sam_sfc.c incorrect EFUSEIOC name used 2024-10-25 08:42:40 +08:00
wangmingrong1 f11b04fc61 kconfig: Add link parameters that can print remaining memory information
LD: nuttx
Memory region         Used Size  Region Size  %age Used
           flash:      284272 B       512 KB     54.22%
           sram1:       13296 B         2 MB      0.63%
           sram2:          0 GB         2 MB      0.00%
CP: nuttx.hex
CP: nuttx.bin

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-10-25 00:55:50 +08:00
Tiago Medicci Serrano a63c807353 esp32s3: Increase the init task stask size when using NSH
After recent changes on nuttx-apps (not limited to, but related
to nuttx-apps#2738, for instance), the stack usage for the NSH
task increased, causing stack overflows under specific situations
(when running `ps` command, for instance). This commit increases
the init task stack size to avoid it. Please note that, even before
these changes, the stack usage of the NSH task was around 90% and,
then, increasing the stack size of it was recommended.
2024-10-25 00:53:21 +08:00
Tim Hardisty bc0f90659f Fix cdcncm printf formatter compiler warning 2024-10-25 00:52:29 +08:00
buxiasen 974db76cb9 sim/cmake: compatible when nuttx COMPILE_OPTIONS is not set yet
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2024-10-24 21:42:06 +08:00
cuiziwei 7bf6325de6 Fix xtensa build error with choice LIBSUPCXX by default.
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-10-24 21:33:20 +08:00
Felipe Moura d291ed0afd Writing documentation related to SPI slave.
Fix build issues
2024-10-24 20:56:36 +08:00
wangmingrong1 d007193eef armv8m/clang.cmake: add armv8m clang config
Its makefile is implemented in arch/arm/src/armv8-m/Toolchain.defs as follows:
ifeq ($(CONFIG_ARM_TOOLCHAIN_CLANG),y)

  ifeq ($(CONFIG_ARCH_CORTEXM23),y)
    TOOLCHAIN_CLANG_CONFIG = armv8m.main_soft_nofp
  else ifeq ($(CONFIG_ARCH_CORTEXM33),y)
    ifeq ($(CONFIG_ARCH_FPU),y)
      TOOLCHAIN_CLANG_CONFIG = armv8m.main_hard_fp
    else
      TOOLCHAIN_CLANG_CONFIG = armv8m.main_soft_nofp
    endif
  else ifeq ($(CONFIG_ARCH_CORTEXM35P),y)
    ifeq ($(CONFIG_ARCH_FPU),y)
      TOOLCHAIN_CLANG_CONFIG = armv8m.main_hard_fp
    else
      TOOLCHAIN_CLANG_CONFIG = armv8m.main_soft_nofp
    endif
  else ifeq ($(CONFIG_ARCH_CORTEXM55),y)
    ifeq ($(CONFIG_ARCH_FPU),y)
      TOOLCHAIN_CLANG_CONFIG = armv8.1m.main_hard_fp
    else
      TOOLCHAIN_CLANG_CONFIG = armv8.1m.main_soft_nofp_nomve
    endif
  else ifeq ($(CONFIG_ARCH_CORTEXM85),y)
    ifeq ($(CONFIG_ARCH_FPU),y)
      TOOLCHAIN_CLANG_CONFIG = armv8.1m.main_hard_fp
    else
      TOOLCHAIN_CLANG_CONFIG = armv8.1m.main_soft_nofp_nomve
    endif
  endif

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-10-24 18:41:11 +08:00
zhangshoukui 1af82ba979 mmcsd: SDIO_CAPS_4BIT_ONLY set buswidth MMCSD_SCR_BUSWIDTH_4BIT
uint8_t buswidth:4;              /* Bus widths supported (SD only) */

Signed-off-by: zhangshoukui <zhangshoukui@xiaomi.com>
2024-10-24 18:06:22 +08:00
Michal Lenc d8ed88c8a6 samv7: fix QSPI build
Commit 313d6df7 caused the following build error:

CC:  fixedmath/lib_b16atan2.c chip/sam_qspi.c: In function 'qspi_memory':
chip/sam_qspi.c:1552:7: warning: implicit declaration of function 'IS_ALIGNED' [-Wimplicit-function-declaration]
 1552 |       IS_ALIGNED((uintptr_t)meminfo->buffer, 4) &&
      |       ^~~~~~~~~~
In file included from chip/sam_qspi.c:41:
chip/sam_qspi.c: In function 'qspi_alloc':
chip/sam_qspi.c:1591:21: warning: implicit declaration of function 'ALIGN_UP' [-Wimplicit-function-declaration]
 1591 |   return kmm_malloc(ALIGN_UP(buflen, 4));

This was caused by missing include of nuttx.h header defining ALIGN_UP
and IS_ALIGNED.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2024-10-24 18:00:05 +08:00
raiden00pl 77303f389f Documentation: migrate README.txt from boards and fixes for mps boards
migrate some README.txt form boards/ and fixes for mps boards rst
2024-10-24 17:47:10 +08:00
zhanghongyu c3a0155374 arch/Kconfig: remove ARCH_MATH_H if LIBCXX
Because some libraries do require a full libm implementation.

Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
2024-10-24 17:44:22 +08:00
Lup Yuen Lee 25c87746db CI: Enable sim-02 build when we create or update a Complex PR
CI Build Job sim-02 was disabled to reduce our usage of GitHub Runners, to comply with ASF Policy: https://github.com/apache/nuttx/issues/14376#issuecomment-2427837859

However this causes the Scheduled Merge Job to fail, due to reduced CI Checks: https://github.com/NuttX/nuttx/actions/runs/11490041505/job/31980056690#step:7:465

This PR re-enables sim-02 when we create or update a Complex PR.
2024-10-24 10:35:23 +08:00
hujun5 9395669ac0 arm64: fix fvp smp faild to boot
reason:
we should give a busy wait addr

This commit fixes the regression from https://github.com/apache/nuttx/pull/13640

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-24 10:17:48 +08:00
anjiahao b33226d76e coredump: coredump_add_memory_region need use flags
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2024-10-24 08:46:01 +08:00
anjiahao f4d1f56df7 gdbstub:fix typo
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2024-10-24 08:45:21 +08:00
anjiahao f307c1587c serial/gdbstub:Adjust serial port gdbstub Kconfig dependencies
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2024-10-24 08:45:21 +08:00
cuiziwei 12fd5ec472 nuttx: Add LIBSUPCXX_TOOLCHAIN to link the prebuilt library provide by toolchain.
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-10-24 01:38:03 +08:00
Ville Juven 134ecf380b task_exit.c: Add missing sched_note_stop()
A regression from #13728 ; sched_note_stop() is never called for tasks
that exit normally via exit().
2024-10-23 12:08:18 -03:00
Tiago Medicci Serrano d1fd1ed8f6 boards/esp32s3: Merge MCUboot and "simple-boot" linker scripts
To make it easier to keep the linker scripts updated for both
MCUboot and "simple-boot", this commit merges them into a single
linker script with macros to enable/disable specific sections.
2024-10-23 22:26:39 +08:00
Huang Qi f933b1644e boards/risc-v: Remove ref to riscv_internal.h
`riscv_internal.h` is a private chip level header file,
and it should not be included in the board files.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-10-23 22:25:10 +08:00
Ville Juven 7a137f0353 syslog: Don't allow blocking when in signal handler
Blocking while running a signal handler is not advisable, instead write
the log string character by character.

There is also a potential for a deadlock, as discussed in #6618

Note: querying for rtcb->sigdeliver is not 100% ideal, as it only tells
_if_ a signal handler has been queued, not if it is running. However, it
makes syslog safe / usable which is a debug feature anyhow.
2024-10-23 21:14:44 +08:00
Rodrigo Sim e16d1218ae arm/stm32f401rc-rs485: Add support to WS2812 addressable LED
Signed-off-by: Rodrigo Sim <rcsim10@gmail.com>
2024-10-23 09:20:44 -03:00
cuiziwei 60e7a0074d nuttx/arch:Enabling ARCH_MATH_H is required when compiling sim with the 13.2 version of the toolchain.
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-23 20:10:43 +08:00
ligd 662bbeb33e container_of: fix compile failed cause of list.h not support container_of
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-23 20:10:43 +08:00
buxiasen 5c09516a4b lib_gdbstub: fix container of
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-23 20:10:43 +08:00
ligd 4845b9e6e5 bluetooth: fix bt missing header files nuttx/wqueue.h
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-23 20:10:43 +08:00
ligd e73c05718c tls.h: list.h should depends on CONFIG_PTHREAD_ATFORK
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-23 20:10:43 +08:00
cuiziwei 002f3c75e4 nuttx/sim: Fix m64 build error.
LD:  nuttx
 nuttx.rel: in function `ff_dct32_float_sse2':
 (.text+0x66f9e): relocation truncated to fit: R_X86_64_32S against symbol `ff_cos_32' defined in .bss.ff_cos_32 section in nuttx.rel
 (.text+0x66fa7): relocation truncated to fit: R_X86_64_32S against symbol `ff_cos_32' defined in .bss.ff_cos_32 section in nuttx.rel
 (.text+0x672a6): relocation truncated to fit: R_X86_64_32S against symbol `ff_cos_16' defined in .bss.ff_cos_16 section in nuttx.rel
 (.text+0x672ae): relocation truncated to fit: R_X86_64_32S against symbol `ff_cos_16' defined in .bss.ff_cos_16 section in nuttx.rel
 nuttx.rel: in function `ff_imdct_calc_sse':
 (.text+0x67905): relocation truncated to fit: R_X86_64_32S against symbol `ff_cos_64' defined in .bss.ff_cos_64 section in nuttx.rel
 (.text+0x67948): relocation truncated to fit: R_X86_64_32S against symbol `ff_cos_128' defined in .bss.ff_cos_128 section in nuttx.rel
 (.text+0x67988): relocation truncated to fit: R_X86_64_32S against symbol `ff_cos_256' defined in .bss.ff_cos_256 section in nuttx.rel
 (.text+0x679c8): relocation truncated to fit: R_X86_64_32S against symbol `ff_cos_512' defined in .bss.ff_cos_512 section in nuttx.rel
 (.text+0x67a08): relocation truncated to fit: R_X86_64_32S against symbol `ff_cos_1024' defined in .bss.ff_cos_1024 section in nuttx.rel
 (.text+0x67a48): relocation truncated to fit: R_X86_64_32S against symbol `ff_cos_2048' defined in .bss.ff_cos_2048 section in nuttx.rel
 (.text+0x67a88): additional relocation overflows omitted from the output

Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-10-23 20:09:55 +08:00
cuiziwei 7e925dbeaa libxx: C++ low level library select LIBSUPCXX by default.
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-10-23 20:09:16 +08:00
Jukka Laitinen cdd11112fd arch/arm64/src/imx9/imx9_lpspi.c: Small cache operation optimization
There is no need to invalidate the RX buffer before every transfer.
It is never gets dirty, so it is good to invalidate initially after allocation,
and after each transfer.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-10-23 19:46:42 +08:00
Jukka Laitinen 6cadfc16cd arch/arm64/src/imx9/imx9_lpspi.c: Fix 9-16 bit transfers
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-10-23 19:46:42 +08:00
Jinliang Li 52995452e5 arm/build: suppress LOAD RWX linker warning
Add --no-warn-rwx-segments in case of RAM boot mode to linker to
suppress the below warning:
"nuttx has a LOAD segment with RWX permissions"

Signed-off-by: Jinliang Li <lijinliang1@lixiang.com>
2024-10-23 19:38:31 +08:00
lipengfei28 3225aa853f arch/arm64: vector table 2K align
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-10-23 15:15:12 +08:00