Add URL to documentation for convenience.
Our module name should not depend on the folder name.
Comment out default values to show that we use the defaults.
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
It is admittedly not an error to use '-h' but who uses '-h' and cares
about the exit code?
Conversely, it is _very_ important to return an error when a bug in a
script passes wrong arguments to smex.
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Commit 34bb9b7282 ("zephyr: wrapper: build SOF with Zephyr for imx")
broke coherent memory allocations on Intel DSP platforms. Restore the
original code.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Add class definition for cavs passthrough-capture
pipeline, and it can be instantiated as:
Object.Pipeline.passthrough-capture."N" {
format "s16le"
period 1000
time_domain "timer"
channels 2
rate 48000
}
Signed-off-by: Chao Song <chao.song@linux.intel.com>
Add class definition for cavs passthrough-playback
pipeline, and it can be instantiated as:
Object.Pipeline.passthrough-playback."N" {
format "s16le"
period 1000
time_domain "timer"
channels 2
rate 48000
}
Signed-off-by: Chao Song <chao.song@linux.intel.com>
Add class definition for HW Config, HW Config object
can be instantiated as:
Object.Base.hw_config."NAME" {
id 0
mclk_freq 24000000
bclk_freq 4800000
tdm_slot_width 25
}
where NAME is the unique instance name for the hw_config
object within the same alsaconf node, for example, SSP0.
Signed-off-by: Ranjani Sridharan <ranjani.sidharan@linux.intel.com>
Signed-off-by: Chao Song <chao.song@linux.intel.com>
Add class definition for manifest.
Signed-off-by: Ranjani Sridharan <ranjani.sidharan@linux.intel.com>
Signed-off-by: Chao Song <chao.song@linux.intel.com>
Add FE DAI class definition, the FE DAI object can be
instantiated as:
Object.Base.fe_dai."NAME" {
id 0
}
Signed-off-by: Ranjani Sridharan <ranjani.sidharan@linux.intel.com>
Signed-off-by: Chao Song <chao.song@linux.intel.com>
Add class definition for pcm, pcm object
can be instantiated as:
Object.PCM.pcm."N" {
id 2
pcm_name "Headset"
direction "playback"
}
Signed-off-by: Ranjani Sridharan <ranjani.sidharan@linux.intel.com>
Signed-off-by: Chao Song <chao.song@linux.intel.com>
Add class definition for copier widget, it can be
instantiated as:
Object.Widget.copier."N" {
copier_type "host"
cpc 100000
}
Signed-off-by: Chao Song <chao.song@linux.intel.com>
capture
S32_LE without PGA is not supported in alsabat, switch to use
pipe-volume-capture and unblock the CI alsabat test case.
Signed-off-by: Iris Wu <xiaoyun.wu@intel.com>
These proved useful when debugging Zephyr but they're not Zephyr specific.
Use mtrace_printf() because if we're having DMA issues we probably want
to avoid the DMA trace
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Add coverage to log out details during memory allocation, including
successful allocation, and all zone types heap.
Signed-off-by: Keyon Jie <yang.jie@linux.intel.com>
When two streams are started one after the other, 2 DAI_CONFIG
IPC's will be sent before the START trigger. This ends up
configuring the SSP when the first one has already just
configured it and ends up with xruns.
The root cause is that the ssp_set_config() function configures
a set of variables, writes those variables into SSP registers,
and later on does a read-modify-write operation on the TSRE,
RSRE and SSE bits.
If the ssp_set_config is executed more than once, this will
temporarily clear all three bitfields, and temporarily disable
DMA transfers and SSP clocks. Avoid this by checking if the
current state is > COMP_STATE_READY before configuring the
SSP, so that the ssp_set_config() function only modifies SSP
registers once.
Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
We don't need to wait until tasks on all DSP COREs finished, before we
can configure the next interrupt to trigger the next scheduling. Imagine
scenarios that one of the CORE is taking long time to finish a high MCPS
task, we should keep tasks on other COREs freed to be scheduled during
that period.
Calculate and re-configure the interrupt at finish of each CORE, and
re-enable domain on each CORE separately.
Signed-off-by: Keyon Jie <yang.jie@linux.intel.com>
Updates the task->state to reflect the real task status and only do
necessary check in schedule_ll_is_pending().
Signed-off-by: Keyon Jie <yang.jie@linux.intel.com>
Pure comments, no code change. Follow-up to commit 8633d5fd6d ("cavs:
pm: improve PM_RUNTIME_HOST_DMA_L1 documentation")
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Does not silently succeeds when passed variables. Not enabled by default
in the unlikely case it wastes memory with some compiler and/or compiler
flags.
Issue found while testing tracing mismatch #4388
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
gcc10.2 does not see that config->elem_array.count is greater than zero
and complains. This happens only at the -O1 optimization level that is
rarely tested.
```
error: 'bd' may be used uninitialized in this function
[-Werror=maybe-uninitialized]
758 | bd->config &= ~SDMA_BD_CONT;
error: 'width' may be used uninitialized in this function
[-Werror=maybe-uninitialized]
786 | watermark = (config->burst_elems * width) / 8;
| ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~
```
This is preferred over initialization at the top of the function
that hides _all_ warnings including valid ones.
Of course the even better fix would to BOTH declare and initialization
just before the loop, as late as possible just like in any other modern
and safer programming language. However C99 declarations are not allowed
yet; I've added this to the next TSC agenda:
github.com/orgs/thesofproject/teams/steering-committee/discussions/24
```
-693,11 +698,9 @@ static int sdma_prep_desc(struct dma_chan_data *channel,
struct dma_sg_config *config)
{
int i;
- int width;
int watermark;
uint32_t sdma_script_addr;
struct sdma_chan *pdata = dma_chan_get_data(channel);
- struct sdma_bd *bd;
/* Validate requested configuration */
if (config->elem_array.count > SDMA_MAX_BDS) {
-713,6 +716,9 @@ static int sdma_prep_desc(struct dma_chan_data *channel,
pdata->next_bd = 0;
+ struct sdma_bd *bd = &pdata->desc[0]; // or NULL
+ int width = 0;
+
for (i = 0; i < config->elem_array.count; i++) {
bd = &pdata->desc[i];
/* For MEM2DEV and DEV2MEM, buf_addr holds the RAM address
```
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
The use of s32le did not expose any problems on APL, but alsa-bat was
previously reported as failing on JSL. Now that this test was extended
to CML_NOCODEC, we see the same issue. Manual tests with s24le show no
issues.
Let's just use s24le across the board and move on.
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Enable the bclk clock control for SSP2.
Note that this impacts existing GLK-based chromebooks as well as newer
hardware.
Signed-off-by: Brent Lu <brent.lu@intel.com>
Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Set clks_control to (SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_ES |
SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_ES) to enable MCLK/BCLK early start
feature.
Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Define the SSP_CC_MCLK/BCLK_ES bit to be used in SSP_CONFIG_DATA macro
to enable mclk/bclk on hw_params and disable malk/bclk on hw_free.
Signed-off-by: Brent Lu <brent.lu@intel.com>
Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
The current code does not follow recommended programming sequences:
TSRE and RSRE should be set before SSE and conversely cleared before
SSE.
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Some codecs need the SSP bit clock to start before data is provided,
and conversely the bit clock to remain active until the hw_free stage.
For backwards-compatibility with older kernels, the
SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_ES and
SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_ES bitfields are used to set an
internal state in the ssp->clk_active field. This helps deals with the
case where a topology sets these bits but the older kernel does not
make use of the modified IPC.
While we are at it, add clearer info traces for SSP configurations.
Note that the FSYNC only starts when DMA transfers are enabled in the
.trigger stage. This is by-design, the FSYNC will only start if the
FIFO is not empty. During the prepare stages the DMA transfers are not
enabled so the FIFOs are empty.
To enable the FSYNC at an earlier stage, we would need a major surgery
in the SOF architecture, or we would need to start zero-based DMA
transfers.
Co-developed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
MCLK and BCLK can be set/release separately. We can set/release mclk/bclk
more flexible with these helpers.
The helpers are defined after the Linux ones, 'prepare_enable' will
first select the relevant resources then enable the clock
output. Conversely 'disable_unprepare' will stop the clock output then
release the clock resources.
Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Add two clks_control bits. MCLK and/or BCLK will start during hw_params
and stop during hw_free if the corresponding bit is set.
This is tagged as a ABI 3.19 change.
Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
The DAI_CONFIG IPC is currently used both for hw_params and
hw_free. For some DAIs, there are hacky ways with e.g. invalid DMA
channels to indicate a hw_free. Rather than adding a new IPC for
hw_params and hw_free, let's add a flag that indicates if the
DAI_CONFIG is really applied during a hw_params or hw_free stage.
This is tagged as a ABI 3.19 change.
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
when the bclk is not based on the default source, we will thrown an
error message but return the result of the mclk configuration.
Fix by adding an explicit -EINVAL return value.
Reported-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
SOF under Zephyr has switched over to a separate LL scheduler, this
code isn't used any longer, remove it.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
This reverts commit af6655e7fa.
That commit removed disabling interrupts in
pipeline_schedule_triggered() which is usually fine, except if an
xrun happens during pipeline_schedule_copy() which then removes the
task from the scheduler list, it then leads to a DSP exception in
pipeline_schedule_copy() is called for the next pipeline in the list.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Anyone having a performance issue can use the standard
-DCMAKE_BUILD_TYPE=Release. Crashes seem more common.
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Before:
error: unable to open sof.elf for reading: 2
After:
error: unable to open sof.elf for reading: No such file or directory
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
When building SOF with Zephyr, for i.MX, we get the following
error: undefined reference to `z_xtensa_cache_inv'.
i.MX has only one DSP core, so CONFIG_KERNEL_COHERENCE is not set.
Therefore include arch/xtensa/cache.h, where z_xtensa_cache_inv
is defined and implemented, in cases when the kernel is not built in
a mode where all shared data is placed in uncached memory.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
When building SOF with Zephyr for i.MX the following
additional adjustments, to the wrapper, are required:
1. include heapmem variable in .heap_mem section,
otherwise the HEAP_SIZE is duplicated in two sections and
the sdram0 region overflows;
2. no need to split heap into shared and unshared since
we only have 1 DSP core; In this case, the kernel will
never be built in a mode where all shared data is placed
in multiprocessor-coherent (generally "uncached") memory.
3. use simple interrupt_get_irq() to get the Linux interrupt
and later pass it to irq_steer;
4. use Xtensa timer, as we do now with SOF and XTOS.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Use the Zephyr sys/util.h when Zephyr RTOS is used.
While here, remove sof/lib/cpu.h which is not used.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Zephyr already uses main() and has already performed
a lot of initialization before entering SOF.
Split initialization, for i.MX platforms, to make sure
no operation is repeated.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
This patch adds init_done status check at the very end of
cadence_codec_prepare() function. This is needed to know if
codec is fully prepared for the processing or not. Note we don't
do anything with the value read at prepare, we postpone final
verification until copy/process time since some codec variants
require input in order to finish its initialization.
Signed-off-by: Marcin Rajwa <marcin.rajwa@linux.intel.com>
Marc Herbert