ControlBytes section name is given by DEF_EQFIR_COEF macro.
Otherwise, using pipe-eq-fir-volume-playback.m4 in a topology results in
a compilation error.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
No need to write to register MUX when it already has value. Second
write option can't set value and clear register to zero.
Signed-off-by: Zhang Peng <peng.zhang_8@nxp.com>
This patch adds support for L1 DRAM memory. If this
memory is available bootloader will try to power up
as many banks of L1 DRAM memory as the platform supports.
Signed-off-by: Marcin Rajwa <marcin.rajwa@linux.intel.com>
This changes the name of MEMORY_POWER_DOWN_DELAY to MEMORY_POWER_CHANGE_DELAY
as we use it in all power change cases and not only when power gating.
Signed-off-by: Marcin Rajwa <marcin.rajwa@linux.intel.com>
Add macro to allow configuration of min channels in PCM_CAPABILITIES.
The default behavior is not changed.
So far min channels was hardcoded to 2 for pipe-volume-playback but we
need mono for i.MX8ULP configuration.
Notice that we need to use the local macro TCHANNELS_MIN because we
don't want to modify the value of CHANNELS_MIN macro outside
of sof/pipe-volume-playback.m4 file.
Doing so will cause unpredictable behavior for next pipeline
definitions.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Make platform_cpu_freq[], platform_ssp_freq[] and
platform_ssp_freq_sources[] arrays static and constant on multiple
platforms.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
The default hw param channel is 2, this will cause dai_verify_params
error when set channel is 1 on imx8ulp. Add special config for imx8ulp.
Signed-off-by: Zhang Peng <peng.zhang_8@nxp.com>
We expect fclk is 16KHz on imx8ulp, and now it's 48KHz.According to
bclk = mclk / ((DIV + 1) * 2), set SAI_CLOCK_DIV is 0x17.
Also expect mono pcm, then set SAI_TDM_SLOTS is 1
Signed-off-by: Zhang Peng <peng.zhang_8@nxp.com>
In order to work well with bluetooth, we expect mono channel and 16bit
pcm data, then config 16bit sywd one channel for imx8ulp.
Signed-off-by: Zhang Peng <peng.zhang_8@nxp.com>
i.MX8ULP uses a MUX to map DMA channels to IP. We map the SAI channels
for now and need to find a more generic approach to select any IP channels.
Signed-off-by: Zhang Peng <peng.zhang_8@nxp.com>
This is for generic hda machine driver. Dmic is
not included since it is been developing. The gain
module in ipc4 has the function of volume component
in ipc3 and we use it to control volume.
Signed-off-by: Rander Wang <rander.wang@intel.com>
Volume is supported by gain module in ipc4. We need
to set curve_type, curve_duration and init_val for
this module.
Signed-off-by: Rander Wang <rander.wang@intel.com>
.next_tick is updated on each timer run to the time of the next run.
Instead the current version sometimes only updates it to the current
time. Fix the update condition.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
i.MX8ULP platform integrates HIFI4 DSP running at 528MHz.
This patch adds support for platform drivers and general
platforminitialization.
Signed-off-by: Zhang Peng <peng.zhang_8@nxp.com>
Add the file for the platform without irqsteer. Now if the platform
have irqsteer we choose interrupt-irqsteer.c, if not then we choose
interrupt-generic.c
Signed-off-by: Zhang Peng <peng.zhang_8@nxp.com>
Make mu implementation generic. imx8ulp platform has a new version
of mu, then update mu for preparing to support imx8ulp.
Signed-off-by: Zhang Peng <peng.zhang_8@nxp.com>
When the firmware receives a START or RELEASE IPC message, it
immediately triggers all involved components, which starts DMA.
Then it schedules the pipeline task, but since the scheduler can be
already running at that time, the task might be scheduled when DMA
data isn't available yet or has already overflowed. To fix this
change the control flow to also trigger all components from the task
during its first run. Actual data processing then begins with the
next period. Note, that this is currently only possible with
pipelines, using timer-based scheduling. Pipelines, using DMA
interrupts for scheduling are unaffected.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Use bool type for boolean flags, split some too long lines, merge
some needlessly split lines.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
pipeline_task_init() is always called with pipeline_task as its last
parameter. Remove the parameter and use the function explicitly.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Add imx8 platform for local testing.
TODO: Update xtensa-build-zephyr.sh when Zephyr repo
is updated with imx8 support.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
In XTOS SOF, ipc_send_queued_msg() is run by task_main_primary_core().
In Zephyr we need to schedule ipc_send_queued_msg() using a notifier
triggered by the periodic ll_scheduler.
This is similar to commit c194125b83 ("zephyr:
add notifier_register(ipc_send_queued_msg) in task_main_start()")
For i.MX we need to use this temporary fix for SOF_SCHEDULE_LL_DMA, also.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
On i.MX the DMA interrupts are routed via IRQ_STEER.
In order for this to work we need to:
- make any second level interrupts handling go
through interrupt-irqsteer.c;
- use first level interrupt handling from
wrapper.c.
TODO: Implement a driver for the IRQ_STEER in Zephyr,
to replace the legacy code (interrupt-irqsteer.c).
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
For now, zephyr_ll is limited to timer_domain.
For i.MX we use dma_domain, so keep the ll_schedule
from SOF, until we extend the zephyr_ll for DMA_IRQ.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Remove zephyr_ll.c from mandatory files for building
SOF with Zephyr and include it where necessary: in CAVS 1.5,
CAVS 1.8, CAVS 2.0 and CAVS 2.5.
While here, add ll_schedule for BROADWELL and BAYTRAIL
when building SOF with Zephyr.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
As of July 2021 we support (too) many tracing options and this
duplication is unfortunately the only way I found to support them all
while giving the compiler the opportunity to optimize away as many
strings as possible.
Supported configurations:
- Systems with limited memory and zero space for full strings, must use
SOF dictionary only.
- Systems with enough space for all strings to be in memory.
- Anything in between
- Support to duplicate only important message to both the DMA and the
mailbox (the default)
- CONFIG_TRACEM: supports duplicating ALL messages to both the DMA and
the mailbox
- CONFIG_TRACEV: supports deleting verbose statements at compile time to
save space
- CONFIG_TRACE: support turning off all traces at compile-time
- SOF dict trace de-duplication a.k.a. "adaptive filtering"
- Dynamic log levels per component
- Redirection to Zephyr's shared memory tracing that requires full strings.
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
From deep down trace.c:va_tracelog() up to the _log_message() level.
Also rename va_tracelog() to the more specific dma_tracelog()
Preparation to support the DMA trace in Zephyr.
The only functional change in this commit is that DMA messages copied to
the shared memory are not de-duplicated any more (a.k.a "adaptive rate
limiting" or CONFIG_TRACE_FILTERING_ADAPTIVE). These are generally
supposed to be high level hence rare enough; otherwise there is probably
a "bigger problem".
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Preparation to use mtrace_dict_entry() also the _log_message() level too
and not just for very early mtrace_printf() tracing.
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Because it's mostly working now and avoids macro nesting complexity;
there is already #ifdef CONFIG_DW_SPI #elif CONFIG_TRACE
Just for the record this is reverting a very tiny part of
commit cf8e35f860 ("zephyr: init: create a zephyr entry point in SOF.")
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Commit a439ea93f6 ("zephyr: ll-schedule: switch over to a simplified
implementation") replaced ll_schedule.c with zephyr_ll.c when compiling
with Zephyr. So the struct tr_ctx named "ll_tr" is now missing. Declare
it in ll_schedule.c too.
No one noticed that ll_tr was missing because the DMA trace does not
work in Zephyr and the main branch yet.
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Currently when an IPC message arrives, the primary core receives the
interrupt, schedules a task and begins processing the message. If it
identifies, that the message is for another core, it sends an IDC
message to it and waits in a busy loop until the other core completes
processing the message and writes a response into the mailbox. After
that the primary core notifies the host about completing the
processing. This patch lets the processing secondary core notify the
host directly, which also frees the primary core to handle other
tasks instead of waiting in a busy loop.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Daniel Baluta