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memory: add timeout into polling loops 

This patch adds timeout condition into all loops
that monitor power status registers.

Signed-off-by: Marcin Rajwa <marcin.rajwa@linux.intel.com>
This commit is contained in:
Marcin Rajwa 2021-07-28 11:22:03 +02:00 committed by Liam Girdwood
parent 0d35bf84f3
commit b604644c65
1 changed files with 13 additions and 2 deletions
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15
src/platform/intel/cavs/include/cavs/lib/pm_memory.h
View File

@ -26,6 +26,7 @@
#include <stdint.h>
#define MEMORY_POWER_CHANGE_DELAY 256
#define MEMORY_POWER_CHANGE_TIMEOUT (256 * MEMORY_POWER_CHANGE_DELAY)
#if CAVS_VERSION >= CAVS_VERSION_1_8
@ -69,14 +70,19 @@ static inline void cavs_pm_memory_hp_sram_mask_set(uint32_t mask, int segment,
bool enabled)
{
uint32_t expected = enabled ? 0 : mask;
uint32_t delay = 0;
io_reg_update_bits(SHIM_HSPGCTL(segment), mask, enabled ? 0 : mask);
io_reg_update_bits(SHIM_HSRMCTL(segment), mask, enabled ? 0 : mask);
idelay(MEMORY_POWER_CHANGE_DELAY);
while ((io_reg_read(SHIM_HSPGISTS(segment)) & mask) != expected)
while ((io_reg_read(SHIM_HSPGISTS(segment)) & mask) != expected) {
idelay(MEMORY_POWER_CHANGE_DELAY);
delay += MEMORY_POWER_CHANGE_DELAY;
if (delay >= MEMORY_POWER_CHANGE_TIMEOUT)
platform_panic(SOF_IPC_PANIC_MEM);
}
}
static inline void cavs_pm_memory_hp_sram_banks_power_gate(
@ -125,6 +131,7 @@ static inline void cavs_pm_memory_lp_sram_banks_power_gate(
{
uint32_t mask = MASK(ending_bank_id, start_bank_id);
uint32_t expected = enabled ? 0 : mask;
uint32_t delay = 0;
shim_write(SHIM_LDOCTL, SHIM_LDOCTL_LPSRAM_LDO_ON);
@ -134,8 +141,12 @@ static inline void cavs_pm_memory_lp_sram_banks_power_gate(
idelay(MEMORY_POWER_CHANGE_DELAY);
while ((io_reg_read(LSPGISTS) & mask) != expected)
while ((io_reg_read(LSPGISTS) & mask) != expected) {
idelay(MEMORY_POWER_CHANGE_DELAY);
delay += MEMORY_POWER_CHANGE_DELAY;
if (delay >= MEMORY_POWER_CHANGE_TIMEOUT)
platform_panic(SOF_IPC_PANIC_MEM);
}
shim_write(SHIM_LDOCTL, SHIM_LDOCTL_HPSRAM_LDO_BYPASS);
}