With Zephyr commit cc5763344709 ("Build system: disable
`OUTPUT_DISASSEMBLY` by default"), generation of zephyr.lst
is disabled by default.
Enable disassembly generation in SOF configuration as it is expected by
SOF builds rules for reproducible builds.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Dell SKU0C87 devices have below config:
SDW0: RT714 DMIC
SDW1: RT1318 Speaker
SDW2: RT1318 Speaker
Add topology support in this patch for Dell SKU0C87 devices.
Signed-off-by: Chao Song <chao.song@linux.intel.com>
Before HOST can request FW to enter D3 state, has to stop all pipelines.
If it's done properly all possible source of IPC messages from FW to
HOST are disabled.
The only exception from this is logger. If logs are enabled FW will
continue to produce new traces and eventually trigger threshold
notification.
This notification is not critical so we can skip it during D3 entry. The
message will remain in the internal list and will be sent when the DSP
wakes up.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch adds build of tplg1 development topologies
sof-tgl-nocodec-crossover-2way.tplg
sof-tgl-nocodec-crossover-4way.tplg
The tplg2 development topology version is
sof-tgl-nocodec-crossover-2way.tplg
Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
Extend the definitions for struct tplg_context and struct tplg_comp_info
to include the fields to parse the ipc_payload and audio format
information from topology.
Also, add the logic for parsing the input/output audio formats from the
topology.
Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
add peak mcps counter to indicate which period have max mcps.
Also changed sample_cnt to period_cnt to make name more sense.
Signed-off-by: Baofeng Tian <baofeng.tian@intel.com>
The script example_crossover.m is converted to export 2, 3, and 4
way crossover configurations for tplg1 and tplg2.
The crossover parameters like number of sinks, pipeline ids of
sinks, sample rate, and band limits are added to generate blob
filenames.
The changes include fixes for running the script with Matlab in
addition to Octave.
Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
In some error situations the configuration init_data may be NULL, and
in such a situations we should fail gracefully and not crash. Also adds
check that the IPC message is of correct type and for IPC3 only that it
is of correct type.
Signed-off-by: Jyri Sarha <jyri.sarha@linux.intel.com>
After commit f639fc8e88 ("copier: rename parent_dev to dev") FW for MTL
platform is not building. This should be detected as merge conflict but it
went unnoticed.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
After dai device was removed, there is no parent device
and dai device classification, only one device left for copier.
The input ipc config is exactly copier device config, no
need extra assignment.
Signed-off-by: Baofeng Tian <baofeng.tian@intel.com>
parent_dev previously used as copier device, and corresponding
child_dev is host and dai, after host and dai device remove,
there is no concept for parent_dev, rename it to dev.
Signed-off-by: Baofeng Tian <baofeng.tian@intel.com>
In ipc3 module creation, it is possible that ipc data
is invalid or corrupted, in this case, module init may crash.
This patch is adding error handling to avoid crash.
Signed-off-by: Baofeng Tian <baofeng.tian@intel.com>
This patch add synchronized FPI updates of HD-A gateways. Driver can
define group of such gateways via module init IPC. The driver may also
specify an update period for each group, different than the default one
determined by the system tick frequency.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch temporary extends comp_ipc_config struct by the value of
input configuration size. Each module receive its own configuration at
creation (MODULE_INIT IPC). In case of a gateway those configuration can
contain additional value (aux_conf). The only way to check if such
config was received is to compare size of the data received via ipc and
standard configuration size.
This solution is temporary because ultimately it would be necessary to
transfer to each module the size of the received configuration along
with a pointer to the configuration itself. Just like the test is in the
case of a module adapter.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This commit changes implementation of DP scheduler
At start point an incorrect assumption has been taken
that it is enough to have one single instance of
DP scheduler located on a primary core
This commit introduces one DP instance per core
Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
SAI can be configured for a one bclk wide frame sync pulse
by setting CR4 SYWD to 0. The REG_SAI_CR4_SYWD()
macro subtracts 1 from its argument which resulted in
bad things happening. So use 1 as correct macro argument.
Signed-off-by: Alexander Boehm <aboehm@eurofunk.com>
The imx SAI driver used hardcoded clock dividers, word lengths
and #ifdefs to deal with differences between SOCs. Changed it
to respect all the SAI_CONFIG parameters.
Signed-off-by: Alexander Boehm <aboehm@eurofunk.com>
Increase PLATFORM_MAX_CHANNELS and PLATFORM_MAX_STREAMS
to 8 in order to enable the use of certain
components (e.g. 'volume') with 8 channels.
This necessitates an increased HEAP_RUNTIME_SIZE.
Signed-off-by: Alexander Boehm <aboehm@eurofunk.com>
No need to check every 250uS for ipc completion, relax this to avoid
any busy scheduling.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
there is no usage for mixin and mixout ipc_config frame
format, remove it in its init function, frame_fmt will be
calculated and assigned in params accordingly, also most of other
modules init funciton does not have this conversion.
Signed-off-by: Baofeng Tian <baofeng.tian@intel.com>
Add virtual heap allocators that allocate on proper heaps and
map physical memory where nesscessary.
Add free function that frees up the virtual heap memory and
unmaps physical memory when possible.
Virtual heap allocator allows using virtual memory as a base
for allocation and booking memory. Physical memory banks
will be mapped when needed allowing for greater flexibility
with mapping.
Signed-off-by: Jakub Dabek <jakub.dabek@intel.com>
In the case of DMA channels using the same IRQ line
the same interrupt handler with different data is
registered multiple times for the same interrupt.
This approach works perfectly fine when using the IRQ_STEER
IP since the way its driver works is it allows registering
multiple handlers+data for the same INTID.
When switching to ARM64, this approach no longer works since
the last irq_handler/irq_data pair will overwrite the previous
one for the same INTID. Because of this, the IRQ bit from the
DMA channel may not get cleared when multiple pipeline tasks
are scheduled. This reasoning applies to the ARM64 architecture
with GICv3 interrupt controller.
To overcome this, the Zephyr DMA domain now holds a list
of channels using the same IRQ. When the DMA IRQ gets triggered,
the handler will iterate through the list of channels using the
same IRQ and clear the interrupt.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Kai Vehmanen