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SAI: fix DSP_A/B frame sync pulse 

SAI can be configured for a one bclk wide frame sync pulse
by setting CR4 SYWD to 0. The REG_SAI_CR4_SYWD()
macro subtracts 1 from its argument which resulted in
bad things happening. So use 1 as correct macro argument.

Signed-off-by: Alexander Boehm <aboehm@eurofunk.com>
This commit is contained in:
Alexander Boehm 2023-05-31 18:23:23 +02:00 committed by Liam Girdwood
parent 0ba64e98ec
commit a1d321734f
1 changed files with 2 additions and 2 deletions
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4
src/drivers/imx/sai.c
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@ -284,7 +284,7 @@ static inline int sai_set_config(struct dai *dai, struct ipc_config_dai *common_
*/
val_cr2 |= REG_SAI_CR2_BCP;
val_cr4 |= REG_SAI_CR4_FSE;
val_cr4 |= REG_SAI_CR4_SYWD(0U);
val_cr4 |= REG_SAI_CR4_SYWD(1U);
break;
case SOF_DAI_FMT_DSP_B:
/*
@ -292,7 +292,7 @@ static inline int sai_set_config(struct dai *dai, struct ipc_config_dai *common_
* frame sync asserts with the first bit of the frame.
*/
val_cr2 |= REG_SAI_CR2_BCP;
val_cr4 |= REG_SAI_CR4_SYWD(0U);
val_cr4 |= REG_SAI_CR4_SYWD(1U);
break;
case SOF_DAI_FMT_PDM:
val_cr2 |= REG_SAI_CR2_BCP;