Commit Graph

1621 Commits

Author SHA1 Message Date
Keyon Jie d58b35c4e7 ssp: switch to use SCR for BCLK generation.
switch the BCLK generation from shim ssp clock divider to
using SSCR0.SCR, as the divider may lead to jitter.

clear and remove M/N divider part code.

Signed-off-by: Keyon Jie <yang.jie@linux.intel.com>
2016-12-22 16:18:36 +00:00
Keyon Jie 05af7a8a8a dw-dma: fix dsp local memory mapping issue
for DMA controller, we need mask dsp local memory before
setting it to DMAC registers, otherwise, DMAC will locate
to wrong memory address.

Signed-off-by: Keyon Jie <yang.jie@linux.intel.com>
2016-12-09 14:15:25 +00:00
Keyon Jie 5ffc92087a pipeline: clear buffer content to 0s on new
We need clear/reset buffer content to 0s each time
creating a pipeline buffer, to avoid random noise
when using it.

Signed-off-by: Keyon Jie <yang.jie@linux.intel.com>
2016-12-09 13:57:19 +00:00
Sebastien Guiriec ca23f51a30 core: Add dsp-core option for XTENSA compiler
In order to use native XTENSA compiler the core target needs to
be overwite with the good platform. This patch is adding an optional
option in order to be able to overwrite the core selection.

Example:
- Set Xtensa export PATH=$PATH:<PATH>/xtensa/XtDevTools/install/tools/RD-2012.5-linux/XtensaTools
./configure --with-arch=xtensa --with-platform=baytrail --with-dsp-core=CHT_audio_hifiep --with-root-dir=<PATH>/xtensa/XtDevTools/install/tools/RD-2012.5-linux/XtensaTools --host=xtensa CC=xt-xcc OBJCOPY=xt-objcopy OBJDUMP=xt-objdump
make
make bin

Signed-off-by: Sebastien Guiriec <sebastien.guiriec@intel.com>
2016-11-02 16:11:26 +00:00
Sebastien Guiriec d7e0013329 readme: Fix DSP compiler tool directy setting for platform build
In order to set the Root directory of the DSP compiler we should
use --with-root-dir instead of --with-tool-dir

Signed-off-by: Sebastien Guiriec <sebastien.guiriec@intel.com>
2016-10-31 23:31:05 +00:00
Keyon Jie 353b0d34ff platform: baytrail: use package string as the fw version
On the linux driver side, it need get version infomation
from fw, including:

type -- Reef
version -- major.minor
build number
last commit id -- gID

So here we use the package string, which come from git
version, which can provide all those fw version infos.

Signed-off-by: Keyon Jie <yang.jie@linux.intel.com>
2016-10-27 10:11:08 +01:00
Keyon Jie 997e14b7b0 ssp: return after draining finished
To prevent the consequent command arrive when we are
at substates.

Signed-off-by: Keyon Jie <yang.jie@linux.intel.com>
2016-10-24 10:53:22 +01:00
Keyon Jie 677fc76612 ssp: cleanup ssp status
We are using 6 states, 2 of them are substates:
init, idle, running, paused,
draining(sub state when transferring from running to idle)
pausing(substate when transferring from running to paused).

Don't response new command when in substates, only stay in
substates for limited timeout. e.g. 2ms for draing and 1ms
for pausing.

Signed-off-by: Keyon Jie <yang.jie@linux.intel.com>
2016-10-24 10:53:15 +01:00
Keyon Jie 991ea7b034 dai: cleanup dai component status
Only use 4 states for dai component:
init, prepare, runing, paused.

Signed-off-by: Keyon Jie <yang.jie@linux.intel.com>
2016-10-24 10:53:05 +01:00
Keyon Jie fec488d446 dai: add macros for dai tracing
Signed-off-by: Keyon Jie <yang.jie@linux.intel.com>
2016-10-24 10:52:51 +01:00
Liam Girdwood 446fe1af42 ipc: dma: Correct typo for DMA timeout time and units.
100 usecs not 1 msec

Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
2016-10-20 16:05:12 +01:00
Liam Girdwood 5b33175b11 platform: cht: Add support for CHT DMACs and SSP ports
Make sure we initialise the extra SSPs and DMACs for CHT.

Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
2016-10-20 15:51:22 +01:00
Liam Girdwood e00e51697a cht: Add M/N dividers for 19.2MHz
Add some M/N divider entries for 19.2M source clock.

Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
2016-10-20 15:51:22 +01:00
Liam Girdwood eb042a4241 dma: Add DMAC2 for CHT
CHT has 3 DMACs compared to the 2 DMACs on BYT

Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
2016-10-20 15:51:22 +01:00
Liam Girdwood 32ebf0f866 dai: add support for CHT SSP ports
CHT has 6 SSP ports compared to 3 on BYT

Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
2016-10-20 15:10:12 +01:00
Liam Girdwood c55a11cdd6 clk: base frequencies for BYT and CHT are different.
Create a table for each platform with the correct frequencies.

Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
2016-10-19 15:31:41 +01:00
Liam Girdwood 8855ce5b4a build: fix configure naming to use newlib header directory.
The tool-dir naming was a bit ambiguous so rename and fix build-all.sh
to use new name too.

Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
2016-10-18 17:18:16 +01:00
Liam Girdwood 419b086240 configure: use the sof mailing list address
Replace the test email addres with sof mailing list in configure.ac

Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
2016-10-17 16:10:42 +01:00
Liam Girdwood b45d98cee1 dma: set mask on local DSP memory regions.
The DMA controller needs to differentiate between host and DSP memory
regions. This can be done with a mask that is ORed with local DSP memory
locations.

Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
2016-10-17 16:10:31 +01:00
Liam Girdwood 0fe9e33143 host: cleanup formatting.
Some lines > 80 chars.

Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
2016-10-17 16:10:20 +01:00
Liam Girdwood c0dfb4e62a core: initial import of open source DSP firmware
This project provides an open source audio firmware infrastructure for audio
DSPs found on many modern devices. The intention is to allow developers to
create their own codecs, audio processing algorithms and pipelines using
the infrastructure and audio components provided by this project.

The project currently supports the Intel Baytrail and Cherrytrail audio DSP
platforms which use the Xtensa architecture.

The firmware source code is released under the BSD 3 clause licence.

Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
2016-09-22 16:02:43 +01:00