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ssp: switch to use SCR for BCLK generation. 

switch the BCLK generation from shim ssp clock divider to
using SSCR0.SCR, as the divider may lead to jitter.

clear and remove M/N divider part code.

Signed-off-by: Keyon Jie <yang.jie@linux.intel.com>
This commit is contained in:
Keyon Jie 2016-12-22 17:27:55 +08:00 committed by Liam Girdwood
parent 05af7a8a8a
commit d58b35c4e7
4 changed files with 1 additions and 134 deletions
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5
src/drivers/ssp.c
View File

@ -221,7 +221,6 @@ static inline int ssp_set_config(struct dai *dai, struct dai_config *dai_config)
/* clock signal polarity */
switch (dai->config.format & DAI_FMT_INV_MASK) {
case DAI_FMT_NB_NF:
sspsp |= SSPSP_SFRMP;
break;
case DAI_FMT_NB_IF:
break;
@ -253,9 +252,7 @@ static inline int ssp_set_config(struct dai *dai, struct dai_config *dai_config)
return -ENODEV;
}
/* TODO: clock frequency */
//scr = dai_config->mclk / (
sscr0 |= SSCR0_SCR(dai->config.mclk_fs / dai->config.bclk_fs - 1);
/* format */
switch (dai->config.format & DAI_FMT_FORMAT_MASK) {
case DAI_FMT_I2S:

10
src/ipc/intel-ipc.c
View File

@ -530,7 +530,6 @@ static uint32_t ipc_device_set_formats(uint32_t header)
{
struct ipc_intel_ipc_device_config_req config_req;
struct ipc_dai_dev *dai_dev;
int err;
trace_ipc("DsF");
@ -569,15 +568,6 @@ static uint32_t ipc_device_set_formats(uint32_t header)
dai_dev->dai_config.mclk_fs = 256;
dai_dev->dai_config.clk_src = SSP_CLK_EXT;
/* set SSP M/N dividers */
err = platform_ssp_set_mn(config_req.ssp_interface,
25000000, 48000,
dai_dev->dai_config.bclk_fs);
if (err < 0) {
trace_ipc_error("eDs");
goto error;
}
comp_dai_config(dai_dev->dev.cd, &dai_dev->dai_config);
error:

5
src/platform/baytrail/include/platform/platform.h
View File

@ -88,9 +88,4 @@ int platform_boot_complete(uint32_t boot_message);
int platform_init(void);
int platform_ssp_set_mn(uint32_t ssp_port, uint32_t source, uint32_t rate,
uint32_t bclk_fs);
void platform_ssp_disable_mn(uint32_t ssp_port);
#endif

115
src/platform/baytrail/platform.c
View File

@ -89,121 +89,6 @@ int platform_boot_complete(uint32_t boot_message)
return 0;
}
struct ssp_mn {
uint32_t source;
uint32_t bclk_fs;
uint32_t rate;
uint32_t m;
uint32_t n;
};
/* TODO: move over to the PLL instead of M/N */
static const struct ssp_mn ssp_mn_conf[] = {
{25000000, 24, 48000, 1152, 25000}, /* 1.152MHz */
{25000000, 32, 48000, 1536, 25000}, /* 1.536MHz */
{25000000, 64, 48000, 3072, 25000}, /* 3.072MHz */
{25000000, 400, 48000, 96, 125}, /* 19.2MHz */
{25000000, 400, 44100, 441, 625}, /* 17.64MHz */
{19200000, 24, 48000, 3, 50}, /* 1.152MHz */
{19200000, 32, 48000, 2, 25}, /* 1.536MHz */
{19200000, 64, 48000, 4, 25}, /* 3.072MHz */
{19200000, 400, 44100, 441, 480}, /* 17.64MHz */
};
/* set the SSP M/N clock dividers */
int platform_ssp_set_mn(uint32_t ssp_port, uint32_t source, uint32_t rate,
uint32_t bclk_fs)
{
int i;
/* check for matching config in the table */
for (i = 0; i < ARRAY_SIZE(ssp_mn_conf); i++) {
if (ssp_mn_conf[i].source != source)
continue;
if (ssp_mn_conf[i].rate != rate)
continue;
if (ssp_mn_conf[i].bclk_fs != bclk_fs)
continue;
/* match */
switch (ssp_port) {
case 0:
shim_write(SHIM_SSP0_DIVL, ssp_mn_conf[i].n);
shim_write(SHIM_SSP0_DIVH, SHIM_SSP_DIV_ENA |
SHIM_SSP_DIV_UPD | ssp_mn_conf[i].m);
break;
case 1:
shim_write(SHIM_SSP1_DIVL, ssp_mn_conf[i].n);
shim_write(SHIM_SSP1_DIVH, SHIM_SSP_DIV_ENA |
SHIM_SSP_DIV_UPD | ssp_mn_conf[i].m);
break;
case 2:
shim_write(SHIM_SSP2_DIVL, ssp_mn_conf[i].n);
shim_write(SHIM_SSP2_DIVH, SHIM_SSP_DIV_ENA |
SHIM_SSP_DIV_UPD | ssp_mn_conf[i].m);
break;
#if defined CONFIG_CHERRYTRAIL
case 3:
shim_write(SHIM_SSP3_DIVL, ssp_mn_conf[i].n);
shim_write(SHIM_SSP3_DIVH, SHIM_SSP_DIV_ENA |
SHIM_SSP_DIV_UPD | ssp_mn_conf[i].m);
break;
case 4:
shim_write(SHIM_SSP4_DIVL, ssp_mn_conf[i].n);
shim_write(SHIM_SSP4_DIVH, SHIM_SSP_DIV_ENA |
SHIM_SSP_DIV_UPD | ssp_mn_conf[i].m);
break;
case 5:
shim_write(SHIM_SSP5_DIVL, ssp_mn_conf[i].n);
shim_write(SHIM_SSP5_DIVH, SHIM_SSP_DIV_ENA |
SHIM_SSP_DIV_UPD | ssp_mn_conf[i].m);
break;
#endif
default:
return -ENODEV;
}
return 0;
}
return -EINVAL;
}
void platform_ssp_disable_mn(uint32_t ssp_port)
{
switch (ssp_port) {
case 0:
shim_write(SHIM_SSP0_DIVH, SHIM_SSP_DIV_BYP |
SHIM_SSP_DIV_UPD);
break;
case 1:
shim_write(SHIM_SSP1_DIVH, SHIM_SSP_DIV_BYP |
SHIM_SSP_DIV_UPD);
break;
case 2:
shim_write(SHIM_SSP2_DIVH, SHIM_SSP_DIV_BYP |
SHIM_SSP_DIV_UPD);
break;
#if defined CONFIG_CHERRYTRAIL
case 3:
shim_write(SHIM_SSP3_DIVH, SHIM_SSP_DIV_BYP |
SHIM_SSP_DIV_UPD);
break;
case 4:
shim_write(SHIM_SSP4_DIVH, SHIM_SSP_DIV_BYP |
SHIM_SSP_DIV_UPD);
break;
case 5:
shim_write(SHIM_SSP5_DIVH, SHIM_SSP_DIV_BYP |
SHIM_SSP_DIV_UPD);
break;
#endif
}
}
/* clear mask in PISR, bits are W1C in docs but some bits need preserved ?? */
void platform_interrupt_clear(uint32_t irq, uint32_t mask)
{